Abstract: A device for physiological measurement. The device includes at least two terminal units connectable to each other, of which a first terminal unit includes an electric circuit, an ECG-electrode and a first connector assembly having at least one ECG-contact for connecting at least one other ECG-electrode. A second terminal unit includes other ECG-electrodes and a second connector assembly having a counter ECG-contact adapted to be fitted to the ECG-contact of the first connector assembly. The first and second terminal are together arranged to connect the ECG-electrode of each second terminal unit to the electric circuit in the first terminal unit and, as separated, are arranged to enable the use of the function contacts of the first connector assembly.

Abstract: A device for physiological measurement. The device includes at least two terminal units connectable to each other, of which a first terminal unit includes an electric circuit, an ECG-electrode and a first connector assembly having at least one ECG-contact for connecting at least one other ECG-electrode. A second terminal unit includes other ECG-electrodes and a second connector assembly having a counter ECG-contact adapted to be fitted to the ECG-contact of the first connector assembly. The first and second terminal are together arranged to connect the ECG-electrode of each second terminal unit to the electric circuit in the first terminal unit and, as separated, are arranged to enable the use of the function contacts of the first connector assembly.

Abstract: The invention relates to the connecting of an improved, intelligent display device interface to a processor that controls the display device through the display device interface. The arrangement according to the invention comprises a display device, an intelligent connection interface of the display device and a processor controlling the display device. In addition, the arrangement comprises a memory bus connected to the processor in order to realize the signaling between the processor and the display device connection interface, and an adapter circuit for matching the signals between the memory bus and the display device connection interface.