Abstract: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Abstract: A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation with gate voltage (Vgs) at a level that causes Idsat degradation by bias temperature instability (BTI). A second dependence of the saturation current (Idsat) recovery versus gate voltage (Vgs) is also measured for the MOS integrated circuit fabrication process. A recovery voltage threshold value is determined. The recovery voltage threshold value is indicative of Vgs voltages below which BTI recovery occurs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, a BTI recovery factor is calculated based on an amount of time the Vgs of the first MOS transistor is below the recovery voltage threshold value.

Abstract: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Abstract: A method for checking for reliability problems includes measuring, for a MOS integrated circuit fabrication process, a dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). The saturation current (Idsat) degradation versus drain voltage (Vds) is also measured for the MOS integrated circuit process. The measured data points of an amount of time until a threshold degradation occurs versus Vgs divided by Vds is fitted to a curve in order to determine a first expected lifetime equation that is based on Vgs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of this simulation, and the first expected lifetime equation, a first expected lifetime for the first MOS transistor is calculated. If the first expected lifetime is less than a lifetime limit, a warning message is generated.

Abstract: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.

Abstract: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.