Patents by Inventor Kaushal Agarwal
Kaushal Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250094287Abstract: Techniques are disclosed relating to providing protection groups and rapid determination of expired objects and associated storage resources in a cloud-based backup storage context. In various embodiments, the disclosed techniques include generating, by a computing system, incremental backup data for a backup based on protection group information, including a set of cloud-based key-value data store buckets, filter information, and policy information. Disclosed techniques also include rapid determination of expired objects and associated storage resources. Disclosed techniques may advantageously provide a centralized view across buckets, accounts, and regions and allow users to target specific subsets of their data stores for backup, which may improve performance and reduce backup storage costs, relative to traditional techniques.Type: ApplicationFiled: August 30, 2024Publication date: March 20, 2025Applicant: Commvault Systems, Inc.Inventors: Chandan Sajjan Agarwal, Raghav Anand, Aniruddh Poornabodha Bharadwaj, Deepak Chawla, Xia Hua, Woonho Joseph Jung, Michal Stanislaw Ostrowski, Hung Hing Anthony Pang, Kanwaljeet Sachdev, Deepan Balajhi Saravanan, Richa Sehgal, Maadhav Kaushal Shah, Nicholas Gerald Zehender
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Publication number: 20240403048Abstract: Various embodiments include techniques for launching processing work in a computing system. The disclosed techniques include load and store operations that specify a category. The disclosed techniques further include barrier instructions that specify a category. A processing unit of the computing system executes a set of load and store operations that specify various categories. When the processor subsequently executes a barrier instruction that specifies a category, the barrier instruction waits for data for only load and store operations that specify the same category. After the barrier instruction completes execution, the processing unit can launch processes that are dependent on data from load and store operations of the specified category, even if data from load and store operations of other categories is still pending. As a result, the processing unit can launch processes as soon as the relevant data is available without waiting for nonrelevant data.Type: ApplicationFiled: May 30, 2023Publication date: December 5, 2024Inventors: Kaushal AGARWAL, Jonathon Stuart Ramsay EVANS
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Patent number: 11934567Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.Type: GrantFiled: September 7, 2021Date of Patent: March 19, 2024Assignee: NVIDIA CorporationInventors: Jonathon Evans, Kaushal Agarwal
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Publication number: 20230070125Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Jonathon Evans, Kaushal Agarwal
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Patent number: 11132146Abstract: Memory page table invalidations for multiple execution contexts (clients or guests) of a memory system are conventionally queued in a single physical command queue. The multiple execution contexts contend to access the queue, resulting in low performance. Instead of contending with other execution contexts to insert invalidation commands into a single physical command queue, a virtual interface and one or more virtual command queues are allocated to each guest. The execution contexts may simultaneously transmit invalidation commands for the memory system through their respective virtual interface. Additionally, each execution context may also transmit other (less often issued) commands through a hypervisor. Error handling and/or illegal access checks specific to invalidation commands that were previously performed by the hypervisor are now performed by the respective virtual interface(s).Type: GrantFiled: May 29, 2019Date of Patent: September 28, 2021Assignee: NVIDIA CorporationInventors: Kaushal Agarwal, Alexander E. Van Brunt
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Patent number: 11093323Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.Type: GrantFiled: April 15, 2019Date of Patent: August 17, 2021Assignee: NVIDIA CorporationInventors: Ashutosh Pandey, Jay Gupta, Kaushal Agarwal, Justin Bennett, Srinivas Santosh Kumar Madugula
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Publication number: 20200379675Abstract: Memory page table invalidations for multiple execution contexts (clients or guests) of a memory system are conventionally queued in a single physical command queue. The multiple execution contexts contend to access the queue, resulting in low performance. Instead of contending with other execution contexts to insert invalidation commands into a single physical command queue, a virtual interface and one or more virtual command queues are allocated to each guest. The execution contexts may simultaneously transmit invalidation commands for the memory system through their respective virtual interface. Additionally, each execution context may also transmit other (less often issued) commands through a hypervisor. Error handling and/or illegal access checks specific to invalidation commands that were previously performed by the hypervisor are now performed by the respective virtual interface(s).Type: ApplicationFiled: May 29, 2019Publication date: December 3, 2020Inventors: Kaushal Agarwal, Alexander E. Van Brunt
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Publication number: 20200327010Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Ashutosh PANDEY, Jay GUPTA, Kaushal AGARWAL, Justin BENNETT, Srinivas Santosh Kumar MADUGULA
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Patent number: 10754775Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.Type: GrantFiled: December 17, 2018Date of Patent: August 25, 2020Assignee: NVIDIA CorporationInventors: Jay Gupta, Gosagan Padmanabhan, Devesh Mittal, Kaushal Agarwal
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Publication number: 20200174932Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.Type: ApplicationFiled: December 17, 2018Publication date: June 4, 2020Inventors: Jay Gupta, Gosagan Padmanabhan, Devesh Mittal, Kaushal Agarwal