Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.

Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.

Abstract: An electronic design automation method implemented in a computing system is provided for creating a physical connections netlist for a pre-floorplan partitioned design file of 3D integrated circuits. The inputs are a 3D stack defining the topology of multiple dies, and a given design partitioning. The design partitioning defines the logic implemented in each die. The method identifies through-silicon-vias (TSVs), bump pins (BPs) and net connections.

Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.

Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.

Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.

Abstract: The present invention relates to processes for the preparation of (3R, 5R)-7-[2-(4-fluorophenyl)-5-isopropyl-3-phenyl-4-[(4-hydroxy methyl phenyl amino)carbonyl]-pyrrol-1-yl]-3,5-dihydroxy-heptanoic acid hemi calcium salt.

Abstract: The present invention provides a process for the preparation of diphenic acid from phenanthrene which comprises heating phenanthrene and glacial acetic acid, adding drop-wise a pre-determined amount of 30% hydrogen peroxide, heating the resulting mixture after completion of drop wise addition of hydrogen peroxide, distilling the resulting mixture under reduced pressure to make the volume half, cooling the mixture till diphenic acid crystalises out, filtering the cooled mixture and boiling the residue after adding 10% solution of sodium carbonate and activated charcoal, filtering and discarding the residue; acidifying the filtrate with hydrogen chloride; cooling the resultant mixture till more diphenic acid crystallises out; repeating filtration till pure diphenic acid is obtained.

Abstract: The present invention relates to ?-amino acid derivatives as dipeptidyl peptidase-IV inhibitors and the processes for the synthesis of the same. This invention also relates to pharmacological compositions containing the compounds of the present invention, and methods of treating diabetes, especially type 2 diabetes, as well as prediabetes, diabetic dyslipidemia, metabolic acidosis, ketosis, satiety disorders, and obesity. These inhibitors can also be used to treat conditions manifested by a variety of metabolic, neurological, anti-inflammatory, and autoimmune disorders like inflammatory disease, multiple sclerosis, rheumatoid arthritis; viral, cancer and gastrointestinal disorders. The compounds of this invention can also be used for treatment of infertility arising due to polycystic ovary syndrome.

Abstract: The present invention relates to processes for the preparation of (3R, 5R)-7-[2-(4-fluorophenyl)-5-isopropyl-3-phenyl-4-[(4-hydroxy methyl phenyl amino)carbonyl]-pyrrol-1-yl]-3,5-dihydroxy-heptanoic acid hemi calcium salt.

Abstract: The present invention relates to a system and a process for obtaining phenanthrene of about 95% purity from coal tar distilled fraction containing crude phenanthrene by performing fractional distillation at a reduced pressure of 50 mm mercury and at a temperature range of 160-180° C. to obtain first distilled fraction containing acenaphthene and fluorene; a second distillate fraction at a temperature range of 200-230° C. containing phenanthrene, anthracene and traces of carbazole; followed by re-distilling the second distillate fraction at a temperature range of 210-224° C. to finally obtain pure phenanthrene and a residue which is again used for the recovery of residual phenanthrene by re-distillation at a temperature range of 210-224° C.

Abstract: The present invention relates to novel 3-azabicyclo[3.1.0]hexane derivatives as dipeptidyl peptidase-IV inhibitors and the processes for the synthesis of the said compounds. This invention also relates to pharmacological compositions containing the compounds of the present invention, and methods of treating diabetes, especially type 2 diabetes, as well as prediabetes, diabetic dyslipidemia, metabolic acidosis, ketosis, satiety disorders, and obesity. These inhibitors can also be used to treat conditions manifested by a variety of metabolic, neurological, anti-inflammatory, and autoimmune disorders like inflammatory disease, multiple sclerosis, rheumatoid arthritis; viral, cancer and gastrointestinal disorders. The compounds of this invention can also be used for treatment of infertility arising due to polycystic ovary syndrome.

Abstract: The present invention provides a process for the preparation of diphenic acid from phenanthrene which comprises heating phenanthrene and glacial acetic acid, adding drop-wise a pre-determined amount of 30% hydrogen peroxide, heating the resulting mixture after completion of drop wise addition of hydrogen peroxide, distilling the resulting mixture under reduced pressure to make the volume half, cooling the mixture till diphenic acid crystalises out, filtering the cooled mixture and boiling the residue after adding 10% solution of sodium carbonate and activated charcoal, filtering and discarding the residue; acidifying the filtrate with hydrogen chloride; cooling the resultant mixture till more diphenic acid crystallises out; repeating filtration till pure diphenic acid is obtained.

Abstract: The present invention relates to a system and a process for obtaining phenanthrene of about 95% purity from coal tar distilled fraction containing crude phenanthrene by performing fractional distillation at a reduced pressure of 50 mm mercury and at a temperature range of 160-180° C. to obtain first distilled fraction containing acenaphthene and fluorene; a second distillate fraction at a temperature range of 200-230° C. containing phenanthrene, anthracene and traces of carbazole; followed by re-distilling the second distillate fraction at a temperature range of 210-224° C. to finally obtain pure phenanthrene and a residue which is again used for the recovery of residual phenanthrene by re-distillation at a temperature range of 210-224° C.

Abstract: The present invention provides a capacitor having upper and lower electrodes formed of iridium or iridium oxide or combinations thereof. The electrodes are preferably formed using physical vapor deposition. An insulating layer disposed between the electrodes can be a ferroelectric ceramic such as PZT or PLZT.