Abstract: A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.

Abstract: A digital potentiometer includes a circuit containing multiple string arrays, each having a plurality of switching devices connected to an array of resistors. Each input terminal receives a separate digital input code enabling the resistance of one of the arms to be varied without changing the other.

Abstract: A digital potentiometer includes a circuit containing multiple string arrays, each having a plurality of switching devices connected to an array of resistors. Each input terminal receives a separate digital input code enabling the resistance of one of the arms to be varied without changing the other.

Abstract: Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.

Abstract: Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.

Abstract: A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.

Abstract: A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.

Abstract: A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.

Abstract: A method and apparatus comprising (i) a first circuit that may be configured to generate a first and second pulse in response to a reset signal, (ii) a latch circuit that may be configured to generate a first and second latch output in response to (a) the first and second pulses, (b) the reset signal and (c) an input signal and (iii) a third circuit that may be configured to generate a detect output in response to the first and second latch outputs. The detect output may be implemented as a trigger signal having an enabled state indicating a floating voltage is present on the input signal. The first and second latch outputs may be used to indicate the drive strength of the input signal. The enabled state of the detect output may have a floating state other than a standard logic "1" or logic "0".