Patents by Inventor Kaushik A. Kumar

Kaushik A. Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10079151
    Abstract: Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 18, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N Tapily, David L O'Meara, Kaushik A Kumar
  • Publication number: 20170092508
    Abstract: Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Kandabara N. Tapily, David L. O'Meara, Kaushik A. Kumar
  • Patent number: 9153457
    Abstract: A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: October 6, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Vidhya Chakrapani, Akiteru Ko, Kaushik A. Kumar
  • Patent number: 8664012
    Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Richard H. Gaylord, Blaze J. Messer, Kaushik A. Kumar
  • Patent number: 8492295
    Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Publication number: 20130084654
    Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Richard H. Gaylord, Blaze J. Messer, Kaushik A. Kumar
  • Patent number: 8367544
    Abstract: A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Johnathan E. Faltermeier, Stephan Grunow, Kaushik A. Kumar, Kevin S. Petrarca
  • Publication number: 20130012018
    Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Patent number: 8298966
    Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Patent number: 8030157
    Abstract: A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Habib Hichri, Ahmad D. Katnani, Kaushik A. Kumar, Narender Rana, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff
  • Patent number: 8008209
    Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael R. Sievers, Kaushik A. Kumar, Andres F. Munoz, Richard Wise
  • Publication number: 20110092069
    Abstract: A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Johnathan E. Faltermeier, Stephan Grunow, Kaushik A. Kumar, Kevin S. Petrarca
  • Patent number: 7879717
    Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Elbert E. Huang, Kaushik A. Kumar, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg
  • Patent number: 7851919
    Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
  • Patent number: 7833893
    Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephan Grunow, Kaushik A. Kumar, Kevin Shawn Petrarca, Richard Paul Volant
  • Patent number: 7825019
    Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephan Grunow, Kaushik A. Kumar, Kevin Shawn Petrarca, Vidhya Ramachandran
  • Patent number: 7737561
    Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A Kumar, Kelly Malone, Christy S Tyberg
  • Patent number: 7732288
    Abstract: A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Lawrence A. Clevenger, Omer H. Dokumaci, Oleg Gluschenkov, Kaushik A. Kumar, Carl J. Radens, Dureseti Chidambarrao
  • Publication number: 20100133694
    Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
    Type: Application
    Filed: February 5, 2010
    Publication date: June 3, 2010
    Inventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
  • Publication number: 20100136800
    Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.
    Type: Application
    Filed: February 2, 2010
    Publication date: June 3, 2010
    Applicant: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise