Patents by Inventor Kaushik Arun Kumar
Kaushik Arun Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8808562Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.Type: GrantFiled: September 12, 2011Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventors: Yusuke Ohsawa, Hiroto Ohtake, Eiji Suzuki, Kaushik Arun Kumar, Andrew W. Metz
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Patent number: 8809194Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.Type: GrantFiled: March 7, 2012Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Kaushik Arun Kumar
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Patent number: 8592327Abstract: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.Type: GrantFiled: March 7, 2012Date of Patent: November 26, 2013Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Kaushik Arun Kumar
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Patent number: 8551877Abstract: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.Type: GrantFiled: March 7, 2012Date of Patent: October 8, 2013Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Kaushik Arun Kumar
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Publication number: 20130237060Abstract: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Alok RANJAN, Kaushik Arun KUMAR
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Publication number: 20130236989Abstract: A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Alok RANJAN, Kaushik Arun KUMAR
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Publication number: 20130237059Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Alok RANJAN, Kaushik Arun KUMAR
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Publication number: 20130065398Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Yusuke OHSAWA, Hiroto OHTAKE, Eiji SUZUKI, Kaushik Arun KUMAR, Andrew W. METZ
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Publication number: 20120064713Abstract: A method of patterning an insulation layer is described. The method includes preparing a feature pattern in an insulation layer using at least one hard mask layer formed on the insulation layer, where the insulation layer contains a low-k material having a dielectric constant less than the dielectric constant of SiO2. The method further includes removing the at least one hard mask layer to expose a flat field surface of the insulation layer and, following the removing, forming a passivation layer on the flat field surface to protect the insulation layer using gas cluster ion beam (GCIB) irradiation of the insulation layer, wherein the GCIB irradiation is configured to grow or deposit the passivation layer on the flat field surface.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Noel RUSSELL, Douglas M. TRICKETT, Kaushik Arun KUMAR
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Patent number: 8058176Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.Type: GrantFiled: September 26, 2007Date of Patent: November 15, 2011Assignees: Samsung Electronics Co., Ltd., International Business Machines Corproation, Advanced Micro Devices Corporation, Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AGInventors: Wan-jae Park, Kaushik Arun Kumar, Joseph Edward Linville, Anthony David Lisi, Ravi Prakash Srivastava, Hermann Willhelm Wendt
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Publication number: 20090081873Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Wan-jae Park, Kaushik Arun Kumar, Joseph Edward Linville, Anthony David Lisi, Ravi Prakash Srivastava, Hermann Willhelm Wendt
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Patent number: 7358182Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.Type: GrantFiled: December 22, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Heidi Lee Baks, Shyng-Tsong Chen, Timothy Joseph Dalton, Nicholas Colvin Masi Fuller, Kaushik Arun Kumar
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Patent number: 7253098Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.Type: GrantFiled: August 27, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Shyng-Tsong T. Chen, Kaushik Arun Kumar, Stephen Edward Greco, Shom Ponoth, Terry Allen Spooner, David L. Rath, Wei-Tsu Tseng
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Patent number: 7084479Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: GrantFiled: December 8, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Venkata Nitta, Sampath Purushothaman, Robert Rosenburg, Christy Sensenich Tyberg, Roy RongQing Yu