Abstract: Passive listening in wireless communication. An activity sensor device senses a packet. A medium access control (MAC) address parser receives the packet, processes a header of the packet, and activates a MAC device in response to recognizing a MAC address within the header, such that the MAC device is not activated if the MAC address parser does not recognize the MAC address.

Abstract: Conditional activation and deactivation of a microprocessor. A hardware portion of an apparatus performs packet processing on received data, where the hardware portion selectively decodes the received data. A microprocessor performs data processing on decoded data, where the microprocessor is conditionally activated for performing the data processing and is conditionally deactivated when not performing the data processing. An output portion receives processed data and audibly renders the processed data without requiring the microprocessor.

Abstract: Hardware-based beacon processing. A hardware-centric medium access control (MAC) device includes a packet receiver and a beacon processor. The packet receiver receives a plurality of packets comprising at least one beacon packet. The beacon processor receives packets of the plurality of packets and filters out unwanted packets of the plurality of packets without requiring the use of other components of the hardware-centric MAC device and without requiring the use of a microprocessor.

Abstract: A method and apparatus for multi-path channel characterization in a Direct Sequence Spread Spectrum based wireless communication system is provided. The multipath channel is modeled as a tapped delay line FIR filter with L taps corresponding to L paths. A pre-defined training sequence is transmitted over the multipath channel. The received signal is sampled and cross correlations are computed between the samples obtained and the spreading sequence for various time lags to obtain the symbol boundary. Thereafter, a desired set of L cross correlations for L time lags around the symbol boundary is estimated. For this, all the L possible sets of L cross correlations for L time lags around the symbol boundary are considered. The energy in the cross correlations corresponding to each considered set is calculated. The set of L cross correlations having the maximum energy is selected for tap computation. The tap coefficients are estimated by solving a set of L simultaneous linear equations.

Abstract: The present invention provides a method and system for clock and carrier recovery in a direct sequence spread spectrum communication system. The process involves the receiver receiving a digital signal that has been transmitted by a remote transmitter. The method for joint clock and carrier recovery comprises the following steps. The received signal is down-converted and the signal is then converted to digital form. The signal is de-spread to obtain the phase of the signal constellation. The clock error at the receiver is then estimated from the phase error of the signal constellation by means of an optimal linear estimator. The discrete carrier frequency offset of the received signal is then estimated from the estimated clock error. The optimal linear estimator used here for estimating the clock error is also the maximum likelihood estimator.

Abstract: A method and apparatus is provided that computes an optimal estimate of known clock frequency error between the transmitter and receiver using a known pilot signal and the statistics of the noise process. The estimate is computed such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. A tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean.