Patents by Inventor Kaushik Chattopadhyay
Kaushik Chattopadhyay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10242883Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.Type: GrantFiled: June 23, 2017Date of Patent: March 26, 2019Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Publication number: 20180374712Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.Type: ApplicationFiled: June 23, 2017Publication date: December 27, 2018Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Patent number: 9881788Abstract: The embodiments disclosed herein pertain to methods and apparatus for depositing stress compensating layers and sacrificial layers on either the front side or back side of a substrate. In various implementations, back side deposition occurs while the wafer is in a normal front side up orientation. The front/back side deposition may be performed to reduce stress introduced through deposition on the front side of the wafer. The back side deposition may also be performed to minimize back side particle-related problems that occur during post-deposition processing such as photolithography.Type: GrantFiled: May 22, 2014Date of Patent: January 30, 2018Assignee: Lam Research CorporationInventors: Yunsang Kim, Kaushik Chattopadhyay, Gregory Sexton, Youn Gi Hong
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Patent number: 9659783Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: GrantFiled: March 27, 2015Date of Patent: May 23, 2017Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Publication number: 20150340225Abstract: The embodiments disclosed herein pertain to methods and apparatus for depositing stress compensating layers and sacrificial layers on either the front side or back side of a substrate. In various implementations, back side deposition occurs while the wafer is in a normal front side up orientation. The front/back side deposition may be performed to reduce stress introduced through deposition on the front side of the wafer. The back side deposition may also be performed to minimize back side particle-related problems that occur during post-deposition processing such as photolithography.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Lam Research CorporationInventors: Yunsang Kim, Kaushik Chattopadhyay, Gregory Sexton, Youn Gi Hong
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Publication number: 20150200106Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: ApplicationFiled: March 27, 2015Publication date: July 16, 2015Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Patent number: 9018103Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: GrantFiled: September 26, 2013Date of Patent: April 28, 2015Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Publication number: 20150087154Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Publication number: 20130323930Abstract: Provided are methods and systems for forming air gaps in an interconnect layer between adjacent conductive lines. Protective layers may be selectively formed on exposed surfaces of the conductive lines, while structures in between the lines may remain unprotected. These structures may be made from a sacrificial material that is later removed to form voids. In certain embodiments, the structures are covered with a permeable non-protective layer that allows etchants and etching products to pass through during removal. When a work piece having a selectively formed protective layer is exposed to gas or liquid etchants, these etchants remove the sacrificial material without etching or otherwise impacting the metal lines. Voids formed in between these lines may be then partially filled with a dielectric material to seal the voids and/or protect sides of the metal lines. Additional interconnect layers may be formed above the processed layer containing air gaps.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Inventors: Kaushik Chattopadhyay, George A. Antonelli, Pramod Subramonium, Mandyam Sriram, Tighe A. Spurlin
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Patent number: 8430992Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.Type: GrantFiled: April 20, 2010Date of Patent: April 30, 2013Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Bart van Schravendijk
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Patent number: 8317923Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.Type: GrantFiled: April 16, 2010Date of Patent: November 27, 2012Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Bart van Schravendijk, Yongsik Yu, Mandyam Sriram
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Patent number: 8173537Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.Type: GrantFiled: March 29, 2007Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Hui-Jung Wu, Bart van Schravendijk, Kimberly Branshaw
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Patent number: 8124522Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.Type: GrantFiled: April 11, 2008Date of Patent: February 28, 2012Assignee: Novellus Systems, Inc.Inventors: Hui-Jung Wu, Kimberly Shafi, Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Girish Dixit, Bart van Schravendijk, Elizabeth Apen
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Patent number: 8021486Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: January 26, 2010Date of Patent: September 20, 2011Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu
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Patent number: 7727881Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.Type: GrantFiled: February 20, 2007Date of Patent: June 1, 2010Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Bart van Schravendijk
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Patent number: 7727880Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.Type: GrantFiled: February 20, 2007Date of Patent: June 1, 2010Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Bart van Schravendijk, Yongsik Yu, Mandyam Sriram
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Patent number: 7704873Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: March 20, 2007Date of Patent: April 27, 2010Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu
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Patent number: 7576006Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: July 30, 2007Date of Patent: August 18, 2009Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu