Patents by Inventor Kaushik De
Kaushik De has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947885Abstract: In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.Type: GrantFiled: September 22, 2021Date of Patent: April 2, 2024Assignee: SYNOPSYS, INC.Inventors: Meera Viswanath, David Allen, Sabyasachi Das, Kaushik De, Renu Mehra, Godwin R. Maben
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Patent number: 11550979Abstract: A system enhances a system design to incorporate safety measures. The system receives a system design for processing through various stages of design using design tools, for example electronic design automation tools for introducing safety features in a circuit design. The system receives safety requirements for the system design, the safety requirements specifying safety measures for the system design. The system generates from the safety requirements, a safety specification storing a set of commands. The system generates a system design enhanced with safety measures. The enhanced system design it generated for at least a subset of the plurality of tools. A tool processes the generated safety specification to implement safety measures in the system design according to the received safety requirements.Type: GrantFiled: April 20, 2021Date of Patent: January 10, 2023Assignee: Synopsys, Inc.Inventors: Kaushik De, Meirav Nitzan, Stewart Williams
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Patent number: 11467851Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.Type: GrantFiled: November 20, 2020Date of Patent: October 11, 2022Assignee: SYNOPSYS, INC.Inventors: Kaushik De, Rajarshi Mukherjee, Paras Mal Jain, David L. Allen
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Patent number: 11222154Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.Type: GrantFiled: October 5, 2020Date of Patent: January 11, 2022Assignee: Synopsys, Inc.Inventors: Kaushik De, Rajarshi Mukherjee, David L. Allen, Bhaskar Pal, Sanjay Gulati, Gaurav Pratap, Nishant Patel, Malitha Kulatunga, Sachin Bansal
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Publication number: 20210334443Abstract: A system enhances a system design to incorporate safety measures. The system receives a system design for processing through various stages of design using design tools, for example electronic design automation tools for introducing safety features in a circuit design. The system receives safety requirements for the system design, the safety requirements specifying safety measures for the system design. The system generates from the safety requirements, a safety specification storing a set of commands. The system generates a system design enhanced with safety measures. The enhanced system design it generated for at least a subset of the plurality of tools. A tool processes the generated safety specification to implement safety measures in the system design according to the received safety requirements.Type: ApplicationFiled: April 20, 2021Publication date: October 28, 2021Inventors: Kaushik De, Meirav Nitzan, Stewart Williams
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Publication number: 20210110093Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.Type: ApplicationFiled: October 5, 2020Publication date: April 15, 2021Inventors: Kaushik DE, Rajarshi MUKHERJEE, David L. ALLEN, Bhaskar PAL, Sanjay GULATI, Gaurav PRATAP, Nishant PATEL, Malitha KULATUNGA, Sachin BANSAL
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Patent number: 10878153Abstract: Apparatuses and methods for performing domain crossing verification of a register transfer level (RTL) representation of an integrated circuit (IC) that includes a memory block are provided. One example method includes receiving an RTL representation of an IC; automatically inferring one or more memory blocks in the RTL representation of the IC; identifying one or more input ports and one or more output ports of the one or more memory blocks; designating the one or more input ports and the one or more output ports as one or more start points and one or more end points; and performing domain crossing analysis on the RTL representation.Type: GrantFiled: October 9, 2019Date of Patent: December 29, 2020Assignee: SYNOPSYS, INC.Inventors: Dipti Ranjan Senapati, Kaushik De, Fahim Rahim
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Patent number: 10706192Abstract: A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both initial power supply voltage values and reconciled/revised voltage values, which are determined by the main driver voltage levels of each power supply. Initial supply relationships generated using the initial PSTs are then compared with final supply relationships generated using the reconciled PSTs, whereby conflicts are identified when one or more initial supply relationship fails to match a final supply relationship, or when one or more final supply relationship fails to match an initial supply relationship.Type: GrantFiled: March 30, 2018Date of Patent: July 7, 2020Assignee: Synopsys, Inc.Inventors: David L. Allen, Kaushik De
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Patent number: 9886753Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.Type: GrantFiled: November 12, 2014Date of Patent: February 6, 2018Assignee: Synopsys, Inc.Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
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Patent number: 9792394Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value. The enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction.Type: GrantFiled: January 30, 2016Date of Patent: October 17, 2017Assignee: Synopsys, Inc.Inventors: Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit K. Gupta, Rajarshi Mukherjee
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Publication number: 20170053051Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).Type: ApplicationFiled: January 30, 2016Publication date: February 23, 2017Applicant: Synopsys, Inc.Inventors: Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit K. Gupta, Rajarshi Mukherjee
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Patent number: 9529948Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.Type: GrantFiled: October 30, 2014Date of Patent: December 27, 2016Assignee: Synopsys, Inc.Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
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Publication number: 20160180012Abstract: A method for low power verification of a circuit description comprises minimizing a circuit description by creating a plurality of crossover trees, and evaluating each of the plurality of crossover trees to identify circuit description errors, in particular low power circuit description errors. The minimizing may comprise creating a plurality of crossover trees to represent circuit description, wherein each crossover tree has a unique set of selected ports and gates of the circuit description.Type: ApplicationFiled: July 23, 2014Publication date: June 23, 2016Inventors: Dipti Ranjan Senapati, Kaushik De, Rajarshi Mukherjee, Shreedhar Ramachandra
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Publication number: 20150131894Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.Type: ApplicationFiled: November 12, 2014Publication date: May 14, 2015Inventors: Mahantesh Narwade, Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal
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Patent number: 9032339Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.Type: GrantFiled: March 6, 2013Date of Patent: May 12, 2015Assignee: Synopsys, Inc.Inventors: Kaushik De, Kevin M. Harer, Rajarshi Mukherjee, Mahantesh Narwade
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Publication number: 20150121326Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.Type: ApplicationFiled: October 30, 2014Publication date: April 30, 2015Inventors: Kaushik De, Mahantesh Narwade, Rajarshi Mukherjee, Namit Gupta
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Publication number: 20140258954Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: SYNOPSYS, INC.Inventors: Kaushik De, Kevin M. Harer, Rajarshi Mukherjee, Mahantesh Narwade
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Patent number: 8479128Abstract: An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.Type: GrantFiled: March 3, 2011Date of Patent: July 2, 2013Assignee: Synopsys, Inc.Inventors: Kaushik De, Badri P. Gopalan, Dhiraj Goswami
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Publication number: 20120227022Abstract: An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Applicant: Synopsys, Inc.Inventors: Kaushik De, Badri P. Gopalan, Dhiraj Goswami
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Patent number: 7797123Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.Type: GrantFiled: June 23, 2008Date of Patent: September 14, 2010Assignee: Synopsys, Inc.Inventors: Kaushik De, Eduard Cerny, Pallab Dasgupta, Bhaskar Pal, Partha Pratim Chakrabarti