Abstract: In a pipeline, data events generated by a producer application are temporally grouped by using a group identification tag. For each data event, data points are generated and uploaded to a storage and cache at each point of production and consumption. The storage allows a matching of data events between the production point and the consumption point, thereby ensuring that streaming parity is maintained. In cases of mismatch, the cache allows for detecting missing data events, i.e., identifying data events that were generated by an upstream producer application, but not consumed by a downstream consumer. While being agnostic to the transformations applied by the various applications in the pipeline, the embodiments disclosed herein keep track of the output data events and input data events and precisely identify the missing data events.

Abstract: System, apparatus and method for managing knowledge generated from technical data are disclosed.

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract: Disclosed is a device for electrically coupling stocked circuit boards using conductive polymer interconnect material and a spacer element. In one embodiment, coaxial connection is provided by means of an array of wires within undulating metal envelopes. In another embodiment, pins are provided within holes in a plastic spacer. In a third embodiment, wires are laid on a substrate and successive laminations are built up to form the spacer element. In a fourth embodiment, wire arrays are extrusion molded within thermoplastic sheets which are laminated to form the spacer element.

Abstract: A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Abstract: A plurality of optical fibers (14-14E) are interconnected by using connectors each comprising an optoelectronic device (13-13E) adapted to be connected to an end of each optical fiber for converting optical signals to electrical signals and for converting electrical signals to optical signals. Each connector has a first contact (12-12E) having a cylindrical plug end and a cylindrical socket end located on a common axis and a transverse conductor (21) extending transversely to the axis (20) from the first contact and connected to the optoelectronic device of the connector. The plug end of each contact is adapted to fit snugly within the socket end of another first contact, whereby all of the contacts may be connected and arranged along the common axis. Each of the contacts is free to rotate with respect to other contacts to which it is connected; this permits the various optical fibers to extend in different radial directions from the axis.

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract: A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.

Abstract: A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.