Abstract: The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.