Abstract: The present disclosure provides for a multi-ratio switched capacitor power converter. The converter may include one or more power switching networks supporting a plurality of power conversion modes and characterised in that: an input terminal connected to an input power source and an associated input capacitance, an output terminal connected to a load and an associated output capacitance to obtain a desired output voltage or output load current regulation; and a switching network with one or more arrangements of switches. The one or more arrangements can be of at least twelve, ten or nine switches to provide for a multi ratio, multi mode power conversion system that addresses the problems faced by existing power converters.

Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.

Abstract: The present disclosure provides a bidirectional hybrid power converter that may include an input circuit consisting of an input power supply and input capacitor, a plurality of switches connected to each other, to input power supply to a set of passive electronic components, to ground and to an output circuit comprising one or more output terminals, each consisting of an output capacitance. The plurality of switches is connected directly or through passive electronic components in an arrangement to obtain a plurality of power converter networks for battery charging as well as other applications by reuse of a set of plurality of switches. The input power supply and the output load are referred to based on the direction of the power conversion flow, forward or reverse. The first terminal can be connected to both a power source as an input and load as an output.

Abstract: The present disclosure provides for a hybrid DC-DC, Hybrid Variable Switched Capacitor (HVSC) power converter. The converter may include one or more power switching networks supporting a plurality of power conversion modes and characterised in that: an input terminal connected to an input power source and an associated input capacitance, an output terminal connected to a load and an associated output capacitance to obtain a desired output voltage or output load current regulation; and at least six switches, one or more inductors and one or more flying capacitors. The converter addresses the problems faced by inductor-based and inductor-less DC-DC power converters while providing higher power conversion efficiencies alike the inductor-less switched capacitor converters and voltage/current regulation alike the inductor-based power converters in a single power conversion unit and enable a duty cycle-based output voltage/current regulation.

Abstract: The present disclosure relates to a system and method to enable power negotiations between a Quick Charge (QC) power source with no USB power delivery (USBPD) support and a USBPD device. The proposed method identifies the support of USBPD and QC in the devices; determines the possibility of direct communication between the devices over either the D+/D?lines or the CC lines, initiates the power negotiations between USBPD device and QC power source either by translating the USBPD messages on CC line to QC signalling on the D+/D?lines and vice versa, or by handling the USBPD messages independently or combination of both; enable the fast charging of USBPD device till the maximum capacity of QC power source complying with USBPD and QC specifications.

Abstract: System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.

Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.

Abstract: System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.

Abstract: The present disclosure provides a bidirectional hybrid power converter that may include an input circuit consisting of an input power supply and input capacitor, a plurality of switches connected to each other, to input power supply to a set of passive electronic components, to ground and to an output circuit comprising one or more output terminals, each consisting of an output capacitance. The plurality of switches is connected directly or through passive electronic components in an arrangement to obtain a plurality of power converter networks for battery charging as well as other applications by reuse of a set of plurality of switches. The input power supply and the output load are referred to based on the direction of the power conversion flow, forward or reverse. The first terminal can be connected to both a power source as an input and load as an output.

Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.

Abstract: The present disclosure relates to a method for facilitating dynamic power allocation and distribution in a multi-port power sourcing device. The method comprises receiving, by a first set of instructions to be executed on a multi-port power sourcing device, the one or more input parameters at the multi-port power sourcing device. The first set of instructions is executed at the multi-port power sourcing device. The first set of instructions pertains to power distribution and operational decision-making across each of the port of the multi-port power sourcing device. Further, a second set of instructions are executed based on the executed first set of instructions. The second set of instructions is executed to manage operations pertaining to a single port of the plurality of ports of the multi-port power sourcing device. The executed first set of instructions control the second set of instructions via a request-response communication interface.

Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.

Abstract: A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

Abstract: Systems involve a dividing unit configured to divide functionality in digital hardware portion through finite state machines (FSMs), protocol timers and PD message accelerator blocks for reducing code size such that their implementation combined with a low code-size firmware (FW) interacts, using a control unit operatively coupled to the dividing unit, with the hardware portion to provide updates in an USB-PD specification, wherein at least one of the FSMs configured to run at a predefined UI clock frequency to enable low active power to the system, a wake-up unit running at least on 4 times of UI clock frequency and detects data edge on configuration channel line to wake-up the entire system from sleep state, wherein a plurality of standard power saving mechanisms selected from clock gating and frequency reduction for clocks are implemented to enable low power corresponding to the system and bypass paths at each level of implementation.

Abstract: Systems involve a dividing unit configured to divide functionality in digital hardware portion through finite state machines (FSMs), protocol timers and PD message accelerator blocks for reducing code size such that their implementation combined with a low code-size firmware (FW) interacts, using a control unit operatively coupled to the dividing unit, with the hardware portion to provide updates in an USB-PD specification, wherein at least one of the FSMs configured to run at a predefined UI clock frequency to enable low active power to the system, a wake-up unit running at least on 4 times of UI clock frequency and detects data edge on configuration channel line to wake-up the entire system from sleep state, wherein a plurality of standard power saving mechanisms selected from clock gating and frequency reduction for clocks are implemented to enable low power corresponding to the system and bypass paths at each level of implementation.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

Abstract: A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.