Abstract: A data processing device includes a cache. The cache stores data. The data processing device also includes a cache manager. The cache manager monitors use of the cache to obtain cache use data. The cache manager identifies a slot allocation of the cache. The cache manager generates a new slot allocation based on the cache use data and the slot allocation. The cache manager reformats the cache based on the new slot allocation to obtain an updated cache.

Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.

Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.

Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.

Abstract: The described technology is generally directed towards caching and aggregated write operations based on predicted patterns of data transfer operations. According to an embodiment, a system can comprise a memory that can store computer executable components, and a processor that can execute the computer executable components stored in the memory. The components can comprise a pattern identifying component to identify a first pattern of data transfer operations performed on a data store, resulting in an identified first pattern, based on monitored data transfer operations. The components can further comprise a pattern predicting component to predict a second pattern of future data transfer operations performed on the data store, resulting in a predicted second pattern, based on the identified first pattern. The components can further comprise a host adapter to generate a data transfer operation to be performed on the data store based on the predicting the second pattern.

Abstract: The described technology is generally directed towards caching and aggregated write operations based on predicted patterns of data transfer operations. According to an embodiment, a system can comprise a memory that can store computer executable components, and a processor that can execute the computer executable components stored in the memory. The components can comprise a pattern identifying component to identify a first pattern of data transfer operations performed on a data store, resulting in an identified first pattern, based on monitored data transfer operations. The components can further comprise a pattern predicting component to predict a second pattern of future data transfer operations performed on the data store, resulting in a predicted second pattern, based on the identified first pattern. The components can further comprise a host adapter to generate a data transfer operation to be performed on the data store based on the predicting the second pattern.

Abstract: A data processing device includes a cache. The cache stores data. The data processing device also includes a cache manager. The cache manager monitors use of the cache to obtain cache use data. The cache manager identifies a slot allocation of the cache. The cache manager generates a new slot allocation based on the cache use data and the slot allocation. The cache manager reformats the cache based on the new slot allocation to obtain an updated cache.

Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.