Abstract: A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit is coupled across a first capacitor for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit is coupled across a second capacitor for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state.