Abstract: On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact of OCV on clock skew. Next, the embodiments can construct a second set of clock tree topologies for timing sequential circuit elements that are not in the set of critical paths, wherein said constructing can comprise optimizing the second set of clock tree topologies to reduce latency, power consumption, and/or area.

Abstract: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.