Abstract: A method of electronic circuit design includes performing property verification for partitions of a design of an electronic circuit, selecting an outcome for each partition from a plurality of outcome categories, and computing coverage information for each element of the design based on the outcome.

Abstract: A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated within the circuit design. The circuit design is then verified using at least one of the propagated assertions as an assumption.

Abstract: Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using approximate reachability analysis to optimize a circuit model by identifying a plurality of next states for a present state, the plurality of next states capable of being reached from the present state in one transition. The plurality of bits of the next states are compared with a plurality of bits of the present state, and each bit of the present state that is different from at least one next state is changed to variant.

Abstract: A method of electronic circuit design includes performing property verification for partitions of a design of an electronic circuit, selecting an outcome for each partition from a plurality of outcome categories, and computing coverage information for each element of the design based on the outcome.

Abstract: A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.