Patents by Inventor Kavitha Prasad

Kavitha Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210312322
    Abstract: A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: Nishit Shah, Reed Kotler, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe, Sedny S.J Attia, Spenser Don Gilliland
  • Publication number: 20210312267
    Abstract: A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: Nishit Shah, Reed Kotler, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe, Sedny S.J Attia, Spenser Don Gilliland
  • Publication number: 20210312320
    Abstract: A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 7, 2021
    Inventors: Nishit Shah, Reed Kotler, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe, Sedny S.J Attia, Spenser Don Gilliland
  • Publication number: 20210013887
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 10790827
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Patent number: 10649927
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20190131975
    Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
  • Publication number: 20190108145
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Applicant: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Publication number: 20190050361
    Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 14, 2019
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Patent number: 7567566
    Abstract: A method and apparatus to perform aging are described. A method to perform timing comprises receiving an address and retrieving an age zone value associated with the received address. A time is then determined using the retrieved age zone value. The determined time may then be associated with the received address.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Kavitha A. Prasad, Miguel A. Guerrero
  • Patent number: 7152140
    Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory. For example, it may be arranged for a read request to be transmitted to a ternary content addressable memory unit. Data content may then be received from the memory unit in response to the read request, a parity check may be performed on the data content. According to some embodiments, parity information may be masked when the memory unit is queried.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventors: Kin Yip Sit, Kavitha A. Prasad, Miguel Guerrero
  • Publication number: 20050141537
    Abstract: Ethernet systems and methods for auto-learning of MAC addresses and lexicographic lookup of hardware databases are disclosed. An Ethernet network device generally includes a hardware MAC address database containing MAC address entries and a hardware MAC address learning engine in communication with the hardware MAC address database and configured to receive an unresolved source MAC address to be learned and to record the unresolved source MAC address in the hardware MAC address database in a corresponding MAC address entry. The Ethernet network device may also include a hardware lexicographic lookup engine configured to perform hardware lookups of MAC address entries in the hardware MAC address database and to interface with a management application program interface (API) for management of the Ethernet network device.
    Type: Application
    Filed: December 29, 2003
    Publication date: June 30, 2005
    Applicant: Intel Corporation A DELAWARE CORPORATION
    Inventors: Mukesh Kumar, Kavitha Prasad
  • Publication number: 20050047408
    Abstract: A method and apparatus to perform aging are described.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Kavitha Prasad, Miguel Guerrero
  • Publication number: 20050024241
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Application
    Filed: August 24, 2004
    Publication date: February 3, 2005
    Inventors: Ashwani Oberai, Kavitha Prasad, Sreenath Kurupati
  • Publication number: 20040260868
    Abstract: According to some embodiments, a parity check is provided for ternary content addressable memory.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 23, 2004
    Inventors: Kin Yip Sit, Kavitha A. Prasad, Miguel Guerrero
  • Patent number: 6801143
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Ashwani Oberai, Kavitha A. Prasad, Sreenath Kurupati
  • Publication number: 20040001014
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Ashwani Oberai, Kavitha A. Prasad, Sreenath Kurupati