Patents by Inventor KAVYA SREE DUGGIMPUDI

KAVYA SREE DUGGIMPUDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971625
    Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Michael V Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, Haiting Wang, Kavya Sree Duggimpudi, Wang Zheng
  • Publication number: 20200411689
    Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.
    Type: Application
    Filed: June 30, 2019
    Publication date: December 31, 2020
    Inventors: MICHAEL V. AQUILINO, DANIEL JAEGER, MAN GU, BRADLEY MORGENFELD, HAITING WANG, KAVYA SREE DUGGIMPUDI, WANG ZHENG
  • Publication number: 20200373410
    Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.
    Type: Application
    Filed: May 26, 2019
    Publication date: November 26, 2020
    Inventors: TUNG-HSING LEE, SIPENG GU, JIEHUI SHU, HAITING WANG, ALI RAZAVIEH, WENJUN LI, KAVYA SREE DUGGIMPUDI, TAMILMANI ETHIRAJAN, BRADLEY MORGENFELD, DAVID NOEL POWER