Abstract: The RMS database for a semiconductor process line is established on the basis of product groups or categories, wherein all members of a category are linked by a common feature, such as a common basic design or a common basic technology. Common process recipes in a specified category may then be set up only once, thereby reducing the amount of effort for establishing the database. Moreover, new product types may be readily incorporated into the categories, thereby enabling the employment of the already-established category-specific context information.

Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.

Abstract: In a production line, a cluster tool having a plurality of substantially identical process modules and a metrology tool includes a control unit that allows one to receive, store and process information that indicates in which process module which substrates have been processed and which selects, on the basis of the process information, which substrate has to be subjected to a measurement. Advantageously, the substrates are selected so that each process module is represented by a corresponding substrate to be measured in order to reliably monitor the process quality of each process module.

Abstract: The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.

Abstract: For patterning an opening through a patterned material, a coating material, a slow-etch material, and a photoresist material are deposited over the patterned material. The opening is patterned through the photoresist material, and the slow-etch material exposed through the opening is etched away. The photoresist material and the coating material exposed through the opening are then etched away. A remaining portion of the slow-etch hard-mask material and the patterned material exposed through the opening are then etched away such that the coating material outside of the opening is exposed. A remaining portion of the coating material is then etched away with an etch agent that does not etch the patterned material.

Abstract: The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.

Abstract: A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask.

Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.

Abstract: The RMS database for a semiconductor process line is established on the basis of product groups or categories, wherein all members of a category are linked by a common feature, such as a common basic design or a common basic technology. Common process recipes in a specified category may then be set up only once, thereby reducing the amount of effort for establishing the database. Moreover, new product types may be readily incorporated into the categories, thereby enabling the employment of the already-established category-specific context information.

Abstract: Various methods of manufacturing are disclosed. In one aspect, a method of manufacturing is provided that includes forming an anti-reflective coating on a structure on a substrate. A first spacer and a second spacer are formed adjacent to the structure. The first spacer covers a first portion of the substrate and the second spacer covers a second portion of the substrate. The anti-reflective coating is removed while the first and second spacers are left in place to protect the first and second portions of the substrate. The method provides for anti-reflective coating application and removal with reduced risk of active region damage.

Abstract: In a production line, a cluster tool having a plurality of substantially identical process modules and a metrology tool comprise a control unit that allows one to receive, store and process information that indicates in which process module which substrates have been processed and which selects, on the basis of the process information, which substrate has to be subjected to a measurement. Advantageously, the substrates are selected so that each process module is represented by a corresponding substrate to be measured in order to reliably monitor the process quality of each process module.

Abstract: A method is presented to increase, by means of dummy via or contact structures, the open areas to 5% or more of the total wafer area in a semiconductor manufacturing process, e.g., contact/via etch processes for interconnect layers. An open area of 5% or more allows robust endpoint detection using optical emission from the plasma, or electrical signals from the RF system. An end-pointed via/contact etch process overcomes the problems encountered due to the effects of aspect-ratio dependent etching, etch rate differences between tools, etch rate fluctuations over time, and deviations of mean incoming film thickness. With end-pointed etching, only the sources of non-uniformity over the wafer have to be considered during etch, which reduces the amount of over-etch built into a conventional via/contact etch process. The dummy structures may be redundant (functional) structures or “true” dummy (non-functional) structures. The dummy structures have the same size as functional structures.

Abstract: Various circuit structures incorporating masks and anti-reflective coatings and methods of fabricating the same are provided. In one aspect, a circuit structure is provided that includes a substrate and a first photosensitive film on the substrate. The first photosensitive film is photosensitive to a first electromagnetic spectrum and anti-reflective of a second electromagnetic spectrum that differs from the first electromagnetic spectrum. A second photosensitive film is on the first photosensitive film. The second photosensitive film is photosensitive to the second electromagnetic spectrum whereby exposure by the second electromagnetic spectrum will activate the second photosensitive film but not the first photosensitive film and exposure by the first electromagnetic spectrum will activate unmasked portions of the first photosensitive film. The first photosensitive film doubles as an anti-reflective coating that may be patterned anisotropically using lithographic techniques.

Abstract: A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.

Abstract: A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.

Abstract: Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.