Patents by Inventor Kay Stephan Essig

Kay Stephan Essig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616007
    Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: March 28, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stephan Essig
  • Patent number: 11462484
    Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: October 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stephan Essig
  • Publication number: 20220115310
    Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stephan ESSIG
  • Publication number: 20220115328
    Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stephan ESSIG
  • Patent number: 8487426
    Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 16, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee
  • Publication number: 20120235309
    Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee