Patents by Inventor Kayamoto Hiroshi

Kayamoto Hiroshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5377138
    Abstract: In a peripheral circuit of a static RAM composed of memory cells of polysilicon high resistance type, there is provided a word line potential deviating circuit which sets the potential of a selected word line during writing operation to be the potential Vvol, the value of which is higher than that of a supplied potential Vdd. The word line potential deviating circuit includes a ring-oscillator circuit, a deviation timing signal generating circuit, a step-up gate control signal generating circuit, a step-up potential generating circuit, a word line supplied potential mixing circuit, and a word line potential supply control circuit.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: December 27, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Kayamoto Hiroshi, Masahiko Nakajima