Patents by Inventor Kayla Chalmers

Kayla Chalmers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080266310
    Abstract: A method, apparatus, and system to scale a color image, the method including determining a color format of image data representative of the color image, the image data being in a pre-processed format and an unprocessed format; and performing a two-dimensional (2-D) image scaling operation on the image data, wherein a plurality of separable one-dimensional filters are applied to the image data to provide a scaled image of the color image and the image scaling operation is the same for the pre-processed formatted image data and the unprocessed formatted image data.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 30, 2008
    Inventors: Kayla Chalmers, Bradley Aldrich
  • Patent number: 7360059
    Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: April 15, 2008
    Assignee: Analog Devices, Inc.
    Inventors: Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Juan G. Revilla, Ravi P. Singh
  • Patent number: 7082516
    Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: July 25, 2006
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Juan G. Revilla, Ravi P. Singh
  • Publication number: 20060149928
    Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
    Type: Application
    Filed: February 3, 2006
    Publication date: July 6, 2006
    Inventors: Thomas Tomazin, William Anderson, Charles Roth, Kayla Chalmers, Juan Revilla, Ravi Singh
  • Publication number: 20050213122
    Abstract: Transfer functions are often used for image processing. Look-up tables can be used to implement transfer functions in a processor-efficient manner. In one embodiment, the invention is an apparatus that includes a look-up table (LUT) storing sample outputs from an output range of a transfer function, the sample outputs corresponding to sample inputs from an input range of the transfer function, the sample inputs being distributed so that more sample inputs are associated with a first region of the transfer function than a second region of the transfer function; and an address module to calculate an index into the LUT based on image data. In one embodiment, the apparatus uses the LUT to process the image data.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 29, 2005
    Inventors: Bradley Aldrich, Moinul Khan, Kayla Chalmers
  • Publication number: 20050024981
    Abstract: A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.
    Type: Application
    Filed: September 1, 2004
    Publication date: February 3, 2005
    Inventors: Robert Bateman, James Harness, Kayla Chalmers