Abstract: A load board includes an electronic component and first wiring connected thereto. A power supply board includes a DC/DC converter and second wiring connected thereto. A bus block includes prismatic block-shaped conductors arranged with a gap interposed therebetween and fixed. The bus block is held between the first plate member and the second plate member such that the end faces of the block-shaped conductors are in contact with the load board and the power supply board. The bus block is connected to the first wiring and the second wiring such that current flows in a direction from the power supply board to the load board in one of two adjacent block-shaped conductors and that current flows in a direction from the load board to the power supply board in the other block-shaped conductor.

Abstract: A load board includes an electronic component and first wiring connected thereto. A power supply board includes a DC/DC converter and second wiring connected thereto. A bus block includes prismatic block-shaped conductors arranged with a gap interposed therebetween and fixed. The bus block is held between the first plate member and the second plate member such that the end faces of the block-shaped conductors are in contact with the load board and the power supply board. The bus block is connected to the first wiring and the second wiring such that current flows in a direction from the power supply board to the load board in one of two adjacent block-shaped conductors and that current flows in a direction from the load board to the power supply board in the other block-shaped conductor.

Abstract: A heat sink for cooling a device mounted on a mount board, the heat sink having a plurality of grooves at different heights in a surface opposite a surface in contact with the device.

Abstract: A heat sink for cooling a device mounted on a mount board, the heat sink having a plurality of grooves at different heights in a surface opposite a surface in contact with the device.

Abstract: A processing system having a testing mechanism that can read out data from a memory such as a ROM without increasing the number of logic circuits to simplify the circuit construction by utilizing the testing mechanism. The processing system includes an address register in the testing mechanism of a chip part connected to the memory in parallel with the other registers, a selector for selecting and sending out either test data from the testing mechanisms or read-out data from the memory. A control unit is further provided so as to set a leading address of the data to be read out from the memory to the address register by the shift operation, to switch the selector to send out the read-out data from the memory, and then, to count up the address of the address register in accordance with a data number to read out, and to read out the data from the memory. This processing system can be applied to a system having the testing mechanism of a JTAG circuit and the like.

Abstract: In a processing system having a testing mechanism for implementing a test on a high density packaging printed circuit board, a data storing unit has an object chip component set unit in which information as to at least one object chip component is set in order to designate the object chip component, a data storage for object chip component for holding therein data that should be written into a register of the object chip component, and a data control unit for writing data held in the data storage for object chip component into the register of the object chip component set in the object chip component set unit in a shifting operation, whereby predetermined data may be written in a register in the testing mechanism without causing an increase of the number of registers for setting data or a storage region used to set data therein so as to simplify a system structure or improve an efficiency of a data setting process.

Abstract: A method and system testing device for testing a printed circuit board includes a JTAG circuit provided with a JTAG instruction storage unit for storing a command to control a system logic circuit; and a JTAG data storage unit for storing data used to control the system logic circuit. The system testing device tests the system logic circuit in an LSI by selectively inputting/outputting data to a boundary scan register, a bypass register, the JTAG instruction storage unit, and the JTAG data storage unit.

Abstract: An information processing system has a plurality of information processing units. Each information processing unit has a system console interface control unit (SCI) connected to an information processing unit body (COM) and a service processor (SVP). The plurality of system console interface control units (SCI) are connected each other in a ring fashion. Each system console interface control unit (SCI) has a processing devcice for processing an interface between the self-service processor (SVP0) and the other-information processing unit body (COM1).