Patents by Inventor Kayoko Omoto
Kayoko Omoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7428174Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.Type: GrantFiled: April 17, 2007Date of Patent: September 23, 2008Assignee: Renesas Technology Corp.Inventors: Yasuhiko Taito, Naoki Otani, Kayoko Omoto, Kenji Koda
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Patent number: 7414912Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.Type: GrantFiled: June 21, 2007Date of Patent: August 19, 2008Assignee: Renesas Technology Corp.Inventors: Yasuhiko Taito, Naoki Otani, Kayoko Omoto, Kenji Koda
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Patent number: 7379345Abstract: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.Type: GrantFiled: April 18, 2007Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventor: Kayoko Omoto
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Publication number: 20070242521Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.Type: ApplicationFiled: June 21, 2007Publication date: October 18, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuhiko Taito, Naoki Otani, Kayoko Omoto, Kenji Koda
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Patent number: 7263002Abstract: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.Type: GrantFiled: April 27, 2005Date of Patent: August 28, 2007Assignee: Renesas Technology Corp.Inventor: Kayoko Omoto
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Publication number: 20070195601Abstract: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.Type: ApplicationFiled: April 18, 2007Publication date: August 23, 2007Inventor: Kayoko Omoto
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Publication number: 20070189078Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cell simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cellsType: ApplicationFiled: April 17, 2007Publication date: August 16, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuhiko TAITO, Naoki OTANI, Kayoko OMOTO, Kenji KODA
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Patent number: 7251165Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.Type: GrantFiled: September 1, 2004Date of Patent: July 31, 2007Assignee: Renesas Technology Corp.Inventors: Yasuhiko Taito, Naoki Otani, Kayoko Omoto, Kenji Koda
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Semiconductor memory and control method thereof allowing high degree of accuracy in verify operation
Patent number: 7154787Abstract: In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.Type: GrantFiled: April 13, 2005Date of Patent: December 26, 2006Assignee: Renesas Technology Corp.Inventor: Kayoko Omoto -
Semiconductor memory and control method thereof allowing high degree of accuracy in verify operation
Publication number: 20050248985Abstract: In write/erase verity operations of a memory transistor in a semiconductor memory, control of the semiconductor memory follows the following process. One main bit line is applied to be operative on the select side and another main bit line is applied to be operative on the reference side. On the select side, a sub bit line select transistor is turned on to select a sub bit line having connection to the memory transistor as a target for write/erase verify operations. The target memory transistor is turned on while the other memory transistors connected to the same sub bit line are turned off. On the reference side, a sub bit line select transistor is turned off to bring a sub bit line to a non-selected state.Type: ApplicationFiled: April 13, 2005Publication date: November 10, 2005Applicant: Renesas Technology Corp.Inventor: Kayoko Omoto -
Publication number: 20050243622Abstract: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.Type: ApplicationFiled: April 27, 2005Publication date: November 3, 2005Applicant: Renesas Technology Corp.Inventor: Kayoko Omoto
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Publication number: 20050057972Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.Type: ApplicationFiled: September 1, 2004Publication date: March 17, 2005Applicant: Renesas Technology Corp.Inventors: Yasuhiko Taito, Naoki Otani, Kayoko Omoto, Kenji Koda
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Patent number: 6538930Abstract: A charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; and power supply generation circuit, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation circuit is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.Type: GrantFiled: October 10, 2001Date of Patent: March 25, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Motoharu Ishii, Kayoko Omoto
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Publication number: 20020089889Abstract: There is a provided a charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; power supply node for receiving a first power supply potential; a first reverse current prevention means connected between the first power supply node and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; and power supply generation means, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation means is formed on or within a semiconductor substrate, and includes a diode element provideType: ApplicationFiled: October 10, 2001Publication date: July 11, 2002Inventors: Motoharu Ishii, Kayoko Omoto
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Patent number: 5043788Abstract: A single chip microcomputer as a semiconductor device comprises CMOS logic portion and a driver portion operating at a high voltage which can be connected to an external device. In the region of the CMOS logic portion, a P type well layer and an N type well layer are formed on a P type silicon substrate. An N type well layer is formed in the region constituting the driver portion. The junction depth of the N type well layer constituting the driver portion is made deeper than that of the N type well layer constituting the CMOS logic portion. A MOS transistor is formed in the region of each well layer in the CMOS logic portion. A MOS transistor whose drain breakdown voltage is increased is formed in the region of the N type well layer of the driver portion. The junction depth of the N type well layer is made deeper than that of the N type well layer constituting the CMOS logic portion at least below the drain region of this MOS transistor.Type: GrantFiled: August 21, 1989Date of Patent: August 27, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kayoko Omoto, Kazuaki Miyata
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Patent number: 4990982Abstract: The semiconductor device is of high break down voltage type and has a source, drain and a gate deposited therebetween on the semiconductor substrate. The gate oxide film has a thick portion and below that portion, a doped layer as a drain is provided with two layers having different impurity concentration.Type: GrantFiled: October 26, 1989Date of Patent: February 5, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kayoko Omoto, Kazuaki Miyata