Abstract: Disclosed is a method for acquiring information on spinal muscular atrophy, comprising acquiring a fluorescence image of a nucleated cell in a measurement sample, wherein the measurement sample is a sample prepared from a blood specimen obtained from a subject, an SMN protein in the nucleated cell is labeled with a first fluorescent dye, and a predetermined nuclear protein in the nucleated cell is labeled with a second fluorescent dye, acquiring an intracellular distance between a first bright spot corresponding to the first fluorescent dye and a second bright spot corresponding to the second fluorescent dye in the fluorescence image, and acquiring a value regarding a number of nucleated cells in which the intracellular distance is equal to or less than a first threshold value, wherein the value is an indicator of spinal muscular atrophy affection.

Abstract: A method is provided which makes it possible to analyze an SMN protein nuclear body that serves as a more highly reliable biomarker. The present method is for analyzing the expression of an SMN protein nuclear body, comprising: labeling one or more surface antigen markers of blood-derived nucleated cells in a sample containing the nucleated cells with one or more label antibodies; labeling SMN protein in the nucleated cells; labeling nuclei of the nucleated cells; selecting one cell population from a plurality of cell populations in which nuclei and SMN protein in the nucleated cells have been labeled and which have been classified based on, e.g., surface antigen markers labeled with label antibodies; and analyzing the expression of an SMN protein nuclear body of the selected cell population based on a label on SMN protein. The method comprises performing imaging flow cytometry using an objective lens with a predetermined magnification.

Abstract: Provided is a method for detecting the expression of SMN protein, said method comprises: a step for labeling SMN protein in a sample, said sample containing nucleated cells derived from blood; a step for labeling the nuclei of the nucleated cells in the sample; a step for selecting a cell population of the nucleated cells in which nuclei and SMN protein are labeled; and a step for detecting the expression of the SMN protein on the basis of the label for the SMN protein in the selected cell population.

Abstract: A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.

Abstract: A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.