Abstract: One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-parity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.

Abstract: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

Abstract: A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked with an interposer interposed therebetween. The logic chip has internal signal/data terminals disposed in its central part and electrically connected to the memory chip. The memory chip includes internal signal/data terminals disposed in its central part, and memory arrays arranged around the internal terminals to surround the same and connected thereto. The internal terminals of the logic chip are connected to the internal terminals of the memory chip via through holes (through electrodes) in the interposer.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal.

Abstract: As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.

Abstract: A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.