Patents by Inventor Kazi Asaduzzaman
Kazi Asaduzzaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10180542Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.Type: GrantFiled: June 30, 2017Date of Patent: January 15, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Samir Aboulhouda, Faouzi Chaahoub, Ahmed Rashid Syed, Kartikeya Gupta, Kazi Asaduzzaman
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Publication number: 20180267257Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.Type: ApplicationFiled: June 30, 2017Publication date: September 20, 2018Inventors: Samir Aboulhouda, Faouzi Chaahoub, Ahmed Rashid Syed, Kartikeya Gupta, Kazi Asaduzzaman
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Patent number: 9136949Abstract: A circuit includes a phase detector circuit and a data detection circuit. The phase detector circuit generates first and second phase detection signals based on a data signal and a periodic signal. The data detection circuit includes logic circuitry that generates a logic signal based on the first and second phase detection signals. The data detection circuit also includes a plurality of delay elements that generate a series of delayed detection signals based on the logic signal. The data detection circuit generates a data detection signal indicating when the data signal contains data based on the series of delayed detection signals.Type: GrantFiled: February 7, 2014Date of Patent: September 15, 2015Assignee: Altera CorporationInventors: Shou-Po Shih, Tim Tri Hoang, Kazi Asaduzzaman
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Patent number: 8829958Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.Type: GrantFiled: December 4, 2012Date of Patent: September 9, 2014Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Tim Tri Hoang, Tin H. Lai, Shou-Po Shih, Sergey Shumarayev
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Patent number: 8811555Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).Type: GrantFiled: February 4, 2010Date of Patent: August 19, 2014Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Tim Tri Hoang, Tin H. Lai, Shou-Po Shih, Sergey Shumarayev
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Patent number: 8671305Abstract: A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.Type: GrantFiled: July 1, 2011Date of Patent: March 11, 2014Assignee: Altera CorporationInventors: Shou-Po Shih, Tim Tri Hoang, Kazi Asaduzzaman
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Patent number: 8120429Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.Type: GrantFiled: May 26, 2010Date of Patent: February 21, 2012Assignee: Altera CorporationInventors: Tim Tri Hoang, Wilson Wong, Kazi Asaduzzaman, Simardeep Maangat, Sergey Shumarayev, Rakesh H. Patel
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Publication number: 20110188621Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.Type: ApplicationFiled: February 4, 2010Publication date: August 4, 2011Inventors: Kazi Asaduzzaman, Tim Tri Hoang, Tin H. Lai, Shou-Po Shih, Sergey Shumarayev
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Patent number: 7728674Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.Type: GrantFiled: May 19, 2006Date of Patent: June 1, 2010Assignee: Altera CorporationInventors: Tim Tri Hoang, Wilson Wong, Kazi Asaduzzaman, Simardeep Maangat, Sergey Shumarayev, Rakesh H. Patel
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Patent number: 7619451Abstract: Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.Type: GrantFiled: February 3, 2007Date of Patent: November 17, 2009Assignee: Altera CorporationInventors: Tim Tri Hoang, Sergey Shumarayev, Kazi Asaduzzaman, Wanli Chang, Mian Z. Smith, Kang-Wei Lai, Leon Zheng
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Patent number: 7602255Abstract: A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.Type: GrantFiled: September 25, 2007Date of Patent: October 13, 2009Assignee: Altera CorporationInventors: Kang-Wei Lai, Ninh D. Ngo, Kazi Asaduzzaman, Mian Z. Smith, Wanli Chang, Tim Tri Hoang
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Patent number: 7557615Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.Type: GrantFiled: February 8, 2008Date of Patent: July 7, 2009Assignee: Altera CorporationInventors: Thungoc M. Tran, Sergey Yuryevich Shumarayev, Kazi Asaduzzaman, Wilson Wong, Mei Luo, Rakesh H. Patel
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Patent number: 7555087Abstract: Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.Type: GrantFiled: February 7, 2008Date of Patent: June 30, 2009Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Wilson Wong
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Patent number: 7532029Abstract: Techniques are provided for dynamically reconfiguring programmable circuit blocks on integrated circuits during user mode. First configuration bits are loaded from first configuration scan registers into second configuration scan registers during configuration mode. The first configuration bits are used to configure programmable settings of a programmable circuit block. During user mode, second configuration bits are transmitted from a pin to the second configuration scan registers without transferring the second configuration bits through the first configuration scan registers. The second configuration bits are used to reconfigure the programmable settings of the programmable circuit block during the user mode. Also, phase shift circuitry can dynamically shift the phase of an output clock signal by selecting a different input clock signal. The phase shift circuitry has a delay circuit that allows the phase of a high frequency clock signal to be shifted without causing glitches in the clock signal.Type: GrantFiled: April 18, 2007Date of Patent: May 12, 2009Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Leon Zheng, Sergey Shumarayev, Tim Tri Hoang
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Patent number: 7355449Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.Type: GrantFiled: February 1, 2006Date of Patent: April 8, 2008Assignee: Altera CorporationInventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Kazi Asaduzzaman, Wilson Wong, Mei Luo, Rakesh Patel
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Patent number: 7352835Abstract: Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.Type: GrantFiled: September 22, 2003Date of Patent: April 1, 2008Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Wilson Wong
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Publication number: 20070013411Abstract: High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Inventors: Kazi Asaduzzaman, Sergey Shumarayev, Thungoc Tran, Wilson Wong, Rakesh Patel
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Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths
Patent number: 7149914Abstract: Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.Type: GrantFiled: September 26, 2003Date of Patent: December 12, 2006Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Wilson Wong, Sergey Shumarayev -
Patent number: 7089444Abstract: Clock and data recovery circuitry is provided that is used in integrated circuits such as programmable logic device integrated circuits. The clock and data recovery circuitry may recover digital data and an embedded clock from a high-speed differential input data stream. The clock and data recovery circuitry may have automatic mode switching capabilities. When operated in reference mode, the clock and data recovery circuit may use a first phase-locked loop to lock onto a reference clock. When operated in data mode, the clock and data recovery circuit may use a second phase-locked loop to lock onto the phase of the differential data stream. A control circuit may automatically switch the clock and data recovery circuit between the reference mode and the data mode. Override signals may be used to force the clock and data recovery circuit out of the automatic mode and into either the reference or data mode.Type: GrantFiled: September 24, 2003Date of Patent: August 8, 2006Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Wilson Wong