Patents by Inventor Kazuaki Furuichi

Kazuaki Furuichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070076577
    Abstract: Provided is a mount structure including: a board; a conductive layer disposed on the board; a protection layer that is disposed on at least the conductive layer, and has first and second apertures disposed within a region in which the conductive layer is disposed; and an electronic component that is mounted on the board, and has a terminal electrically connected to the conductive layer in a region surrounded by a fringe of the first aperture, wherein a region surrounded by a fringe of the second aperture is an alignment mark that is used to match the location of the terminal of the electronic apparatus to the location of the first aperture.
    Type: Application
    Filed: August 10, 2006
    Publication date: April 5, 2007
    Applicant: SANYO EPSON IMAGING DEVICES CORP.
    Inventor: Kazuaki Furuichi
  • Patent number: 6128063
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: October 3, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5986342
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: November 16, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5737272
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: April 7, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda