Patents by Inventor Kazuaki Ishizaki

Kazuaki Ishizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170148132
    Abstract: A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventor: Kazuaki Ishizaki
  • Publication number: 20170147305
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is set to be a default application binary, to be sent to devices requesting the application for a first time, if a percentage of matching application profiles exceeds a threshold. The optimized binary for the application is transmitted to the second device.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Publication number: 20170124677
    Abstract: A method is provided for buffer allocation on a graphics processing unit. The method includes analyzing, by the graphics processing unit, a program to be executed on the graphics processing unit to determine, for an object in the program, a set of elements in the object that are designated to be accessed during an execution of the program. The method further includes allocating, by the graphics processing unit, a placement of the object in a device buffer on the graphics processing unit based on the set of elements to minimize a number of memory accesses during the execution of the program.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 4, 2017
    Inventor: Kazuaki Ishizaki
  • Patent number: 9612810
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is transmitted to the second device.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Publication number: 20170060553
    Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is transmitted to the second device.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
  • Publication number: 20170039231
    Abstract: Methods and a system are provided for accelerating an operation in a B+-tree. A method including forming triplets, by a triplet manager. Each of the triplets includes a pointer to a leaf node, a lower bound of a key on the leaf node, and an upper bound of the key on the leaf node. The method further includes performing, by the triplet manager, a lookup operation on the triplets responsive to the operation to avoid traversals of intermediate nodes for the operation. The method also includes executing, by a processor, the operation in the B+-tree while avoiding the traversals of the intermediate nodes for the operation responsive to a result of the lookup operation. The operation is any one of an insertion operation, a deletion operation, and a search operation.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventor: Kazuaki Ishizaki
  • Publication number: 20170024214
    Abstract: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
    Type: Application
    Filed: October 5, 2016
    Publication date: January 26, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kazuaki Ishizaki
  • Patent number: 9542185
    Abstract: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kazuaki Ishizaki
  • Patent number: 9098319
    Abstract: An improved technique for inserting reference count code in a garbage collection technique. When there are two or more successor basic blocks to a basic block, a given variable is live at the entry of one or more of the successor basic blocks, and the variable is dead in another basic block S, a new basic block is inserted between the original basic block and a successor basic block in which the variable is dead, and RC? related to the variable is generated in the new basic block.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kazuaki Ishizaki
  • Publication number: 20150178375
    Abstract: Exemplary embodiments include methods and systems for searching a tree using an instruction of operating data having predetermined multiple bit widths. Aspects include constructing the tree by classifying nodes of the tree into groups having a minimum bit width capable of representing a value of a key among the multiple bit widths. Aspects further include searching for data in the group having the minimum bit width with a value of a search key being an effective number, using the instruction corresponding to the group having the minimum bit width with the value of the search key being the effective number.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 25, 2015
    Inventor: KAZUAKI ISHIZAKI
  • Patent number: 9027008
    Abstract: A method, computer, and computer program for speculatively optimizing a code. The method includes speculatively optimizing the code characterized by searching in a predetermined order in at least one dictionary; extracting a value associated with a symbol name from a dictionary using the symbol name as a key; performing optimization to replace a symbol in the code with the value; compiling the code to be compiled including some or all of the optimized code; comparing, in response to detection of a change related to one dictionary among at least one dictionary, an order m in the predetermined order of the dictionary with the detected change to an order n of the dictionary with the extracted value; and invalidating the optimized code in the compiled code associated with the dictionary having the detected change in response to the results from the orders comparison and the type of change.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 8972959
    Abstract: A method of converting a program code of a program running in multi-thread to a program code which causes fewer lock collisions. The method includes reading the program code into a memory and searching the program code for a first conditional statement making a branch to a path, which is in a synchronized block and has no side effect on the synchronized block; duplicating the path having no side effect to which the branch is made by the searched first conditional statement into the outside of the synchronized block; and adding a second conditional statement into the program code in response to the duplication, wherein the second conditional statement is a conditional statement making a branch to the duplicated path having no side effect. Also provided is a system and an article of manufacture which causes a computer to carry out the steps of the above method.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Publication number: 20150026433
    Abstract: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 22, 2015
    Inventor: Kazuaki Ishizaki
  • Publication number: 20140082598
    Abstract: An improved technique for inserting reference count code in a garbage collection technique. When there are two or more successor basic blocks to a basic block, a given variable is live at the entry of one or more of the successor basic blocks, and the variable is dead in another basic block S, a new basic block is inserted between the original basic block and a successor basic block in which the variable is dead, and RC? related to the variable is generated in the new basic block.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Applicant: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 8589899
    Abstract: A system, method and article of manufacture of increasing access speed of frequently accessed variables (symbols) in a dynamic language program. The system includes a range identifying unit to identify a range for communizing symbol accesses in the program; an instruction generating unit to generate instructions to access a symbol table using a key, to get an address of a symbol entry, and to store the address; an instruction extracting unit to fetch instructions from the identified range; and an instruction judging unit to determine whether or not each of the fetched instructions is an instruction to access the symbol. If the fetched instruction is an instruction to access the symbol, and the symbol is present when generating an instruction to access the symbol by using an address of the stored symbol entry, an instruction is generated allowing access to the symbol without checking whether the symbol is present.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Publication number: 20130290942
    Abstract: A method, computer, and computer program for speculatively optimizing a code. The method includes speculatively optimizing the code characterized by searching in a predetermined order in at least one dictionary; extracting a value associated with a symbol name from a dictionary using the symbol name as a key; performing optimization to replace a symbol in the code with the value; compiling the code to be compiled including some or all of the optimized code; comparing, in response to detection of a change related to one dictionary among at least one dictionary, an order m in the predetermined order of the dictionary with the detected change to an order n of the dictionary with the extracted value; and invalidating the optimized code in the compiled code associated with the dictionary having the detected change in response to the results from the orders comparison and the type of change.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 31, 2013
    Applicant: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 8572584
    Abstract: A method, computer system, and computer readable article of manufacture for converting a first program code in a multi-threaded program into a second program code which causes less lock contention. A processing unit determines whether the first program code includes either a first class having a method call to a third class that operates while taking synchronization by locking, or a second class inheriting a parent class that operates while taking synchronization by locking. If the first class, then it is converted into a class with a method call to a concurrent operation executable class that is functionally equivalent and a shorter lock holding section. If the second class, then it is converted into a class with a method call to a concurrent operation executable class that is functionally equivalent to that of the parent class, and a shorter lock holding section.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki
  • Patent number: 8296747
    Abstract: A system acquires an output program for sequentially executing a plurality of character string output instructions, and thereby for outputting a text in which a plurality of output character strings are combined. The system converts the character code set of the character string constants, which is outputted by at least one of the character string output instructions, from a first code set for internal processing to a second code set for output, before the output program is executed. In addition, the system buffers the values of two or more character string variables to be outputted by two or more of the character string output instructions without converting the character code set from the first code set, during the execution of the output program.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kazuaki Ishizaki, Goh Kondoh
  • Patent number: 8271587
    Abstract: An object movement control system, an object movement control method, a server, and a computer program that can update the positional information of an object in a virtual space at high speed by appropriately distributing processing loads. Client control units obtain information about the position of a first object in a virtual space and information about movement of the first object and detect other objects that exist in a virtual region that contains the first object, which has been moved. The distances between objects that exist in a virtual region are calculated, and only when the number of objects the distances to which are shorter than a predetermined threshold exceeds a predetermined number, information about the objects is sent to a server. The server assigns a collision determination client that performs collision determination to each pair of objects selected from the objects.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kazuaki Ishizaki, Shuichi Shimizu
  • Publication number: 20120054470
    Abstract: A system, method and article of manufacture of increasing access speed of frequently accessed variables (symbols) in a dynamic language program. The system includes a range identifying unit to identify a range for communizing symbol accesses in the program; an instruction generating unit to generate instructions to access a symbol table using a key, to get an address of a symbol entry, and to store the address; an instruction extracting unit to fetch instructions from the identified range; and an instruction judging unit to determine whether or not each of the fetched instructions is an instruction to access the symbol. If the fetched instruction is an instruction to access the symbol, and the symbol is present when generating an instruction to access the symbol by using an address of the stored symbol entry, an instruction is generated allowing access to the symbol without checking whether the symbol is present.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Applicant: International Business Machines Corporation
    Inventor: Kazuaki Ishizaki