Patents by Inventor Kazuaki Iwasawa
Kazuaki Iwasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8900984Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.Type: GrantFiled: April 12, 2013Date of Patent: December 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Nakao, Kazuaki Iwasawa
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Patent number: 8723245Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.Type: GrantFiled: March 21, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Kiyohito Nishihara, Masaki Kondo, Yingkang Zhang, Shigeo Kondo, Hidenobu Nagashima, Kazuaki Iwasawa, Takashi Ichikawa
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Publication number: 20130237047Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.Type: ApplicationFiled: April 12, 2013Publication date: September 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Nakao, Kazuaki Iwasawa
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Patent number: 8441061Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.Type: GrantFiled: August 25, 2010Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Nakao, Kazuaki Iwasawa
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Patent number: 8329553Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.Type: GrantFiled: March 23, 2010Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Shogo Matsuo, Takeshi Hoshi, Keisuke Nakazawa, Kazuaki Iwasawa
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Patent number: 8193056Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes the steps of: forming a tunnel insulating film on a semiconductor substrate; forming a floating gate electrode on the tunnel insulating film; and forming a silicon nitride film including a low-density silicon nitride film and a high-density silicon nitride film on the floating gate electrode. The method also includes the steps of: forming an isolation trench thereby to expose the low-density silicon nitride film exposed at least in a portion of a side surface of the isolation trench; forming an isolating insulating film covering an internal surface of the isolation trench; removing the silicon nitride film; and forming an interelectrode insulating film and a control gate electrode both covering the floating gate electrode and the isolating insulating film.Type: GrantFiled: September 9, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Iwasawa, Shogo Matsuo, Kenichiro Toratani
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Publication number: 20120034754Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
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Publication number: 20120018783Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode.Type: ApplicationFiled: May 27, 2011Publication date: January 26, 2012Inventors: Kazuaki Iwasawa, Shigeo Kondo, Hiroshi Akahori, Kiyohito Nishihara, Yingkang Zhang, Masaki Kondo, Hidenobu Nagashima, Takashi Ichikawa
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Publication number: 20120018780Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.Type: ApplicationFiled: March 30, 2011Publication date: January 26, 2012Inventors: Kazuaki Iwasawa, Shigeo Kondo, Hiroshi Akahori, Kiyohito Nishihara, Yingkang Zhang, Masaki Kondo, Hidenobu Nagashima, Takashi Ichikawa
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Publication number: 20120007163Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.Type: ApplicationFiled: March 21, 2011Publication date: January 12, 2012Inventors: Hiroshi Akahori, Kiyohito Nishihara, Masaki Kondo, Yingkang Zhang, Shigeo Kondo, Hidenobu Nagashima, Kazuaki Iwasawa, Takashi Ichikawa
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Patent number: 8080463Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.Type: GrantFiled: January 21, 2010Date of Patent: December 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
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Publication number: 20110065271Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes the steps of: forming a tunnel insulating film on a semiconductor substrate; forming a floating gate electrode on the tunnel insulating film; and forming a silicon nitride film including a low-density silicon nitride film and a high-density silicon nitride film on the floating gate electrode. The method also includes the steps of: forming an isolation trench thereby to expose the low-density silicon nitride film exposed at least in a portion of a side surface of the isolation trench; forming an isolating insulating film covering an internal surface of the isolation trench; removing the silicon nitride film; and forming an interelectrode insulating film and a control gate electrode both covering the floating gate electrode and the isolating insulating film.Type: ApplicationFiled: September 9, 2010Publication date: March 17, 2011Inventors: Kazuaki IWASAWA, Shogo MATSUO, Kenichiro TORATANI
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Publication number: 20110057249Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.Type: ApplicationFiled: August 25, 2010Publication date: March 10, 2011Inventors: Takashi NAKAO, Kazuaki Iwasawa
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Publication number: 20100311220Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.Type: ApplicationFiled: March 23, 2010Publication date: December 9, 2010Inventors: Shogo MATSUO, Takeshi Hoshi, Keisuke Nakazawa, Kazuaki Iwasawa
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Patent number: 7803721Abstract: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.Type: GrantFiled: March 14, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Iwasawa
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Publication number: 20100190317Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.Type: ApplicationFiled: January 21, 2010Publication date: July 29, 2010Inventors: Kazuaki IWASAWA, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
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Patent number: 7582572Abstract: A method of manufacturing an insulating film includes coating a first liquid material in which polysilazane is dissolved on a substrate; decreasing dangling bonds of silicon (Si) in the first liquid material; after decreasing the dangling bonds, coating a second liquid material which is similar to the first liquid material on the first liquid material; and converting the first liquid material and the second liquid material into a silicon (Si) insulating film.Type: GrantFiled: December 14, 2006Date of Patent: September 1, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Iwasawa
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Publication number: 20070284649Abstract: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.Type: ApplicationFiled: March 14, 2007Publication date: December 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuaki IWASAWA
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Publication number: 20070196966Abstract: A method of manufacturing an insulating film includes coating a first liquid material in which polysilazane is dissolved on a substrate; decreasing dangling bonds of silicon (Si) in the first liquid material; after decreasing the dangling bonds, coating a second liquid material which is similar to the first liquid material on the first liquid material; and converting the first liquid material and the second liquid material into a silicon (Si) insulating film.Type: ApplicationFiled: December 14, 2006Publication date: August 23, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kazuaki IWASAWA
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Publication number: 20070103064Abstract: An electroluminescent display has a transparent substrate. A transparent positive electrode is formed on the transparent substrate. An inert metal film is formed on the transparent positive electrode. A hole transport layer on the inert metal film, includes a conductive polymer doped with a polymeric electrolyte containing a sulfone group. An emissive layer is formed on the hole transport layer.Type: ApplicationFiled: December 22, 2006Publication date: May 10, 2007Inventors: Kazuaki Iwasawa, Hideki Ookawa