Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.

Abstract: According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.

Abstract: According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.

Abstract: A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or non-selected, based on an input signal. They also include an address signal input section configured to provide a signal to address the memory chip, based on an input signal. They further include a select address signal input section configured to make the plurality of memory chips selected or non-selected, based on an input signal, and configured divertible to the address signal input section.

Abstract: A semiconductor device includes plural memory cell blocks, each having a memory array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/.output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.

Abstract: A semiconductor device includes plural memory cell blocks, each having a memory cell array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.

Abstract: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or non-selected, based on an input signal. They also include an address signal input section configured to provide a signal to address the memory chip, based on an input signal. They further include a select address signal input section configured to make the plurality of memory chips selected or non-selected, based on an input signal, and configured divertible to the address signal input section.

Abstract: Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell. A first determination circuit compares the normal data read from the data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. A second determination circuit compares the parity data read from the parity data lines and their expectation value, respectively, and determines whether the data and the expectation value coincide, respectively. The second determination circuit includes a selection circuit that selectively outputs a determination result on a part of the parity data lines.

Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: A semiconductor device that generates a desired internal power supply by using, as a reference potential, a potential obtained by adjusting a preset standard potential, the semiconductor device comprises; a reference potential selection circuit selecting the reference potential on the basis of digital data from among a plurality of potentials of different levels which are obtained by dividing a power supply voltage, and outputting the reference potential instead of the standard potential; a first decision circuit deciding bits of the digital data; a second decision circuit deciding the bits of the digital data, separately from the first decision circuit; and a data transfer circuit transferring to the reference potential selection circuit the digital data which is decided by either one of the first and second decision circuits.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.