Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At least a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Abstract: A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer.

Abstract: In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-gate region while a nitride film is formed or dry cleaning is carried out over the semiconductor surface of an inter-gate-drain region, in order that surface traps in the semiconductor surface of the inter-gate-drain region, which is not covered with electrode metal, is greater in number than those in the semiconductor surface of the inter-source-gate region.

Abstract: In a field effect transistor, a semiconductor channel layer is formed for carriers to run therein, and a first conductive semiconductor carrier supply layer is formed on the channel layer. Also, a second conductive semiconductor layer has a conductive type opposite to the carrier supply layer or contacts the gate electrode and is formed of same materials as the carrier supply layer. A third conductive semiconductor layer is formed on the layer having a conductive type opposite to the carrier supply layer or contacting the gate electrode and has the same conductive type of the carrier supply layer. A schottky gate electrode is formed in contact with the second conductive semiconductor layer.

Abstract: A frequency compensator is disposed as a stage preceding an inverter or a source follower constituted by a compound semiconductor FET, and it has a node A, at which an input signal is divided by resistances, and a node B, at which the input signal is divided by capacitances. The two nodes A and B are connected to each other via a diode such that the diode is biased forward when the node A is biased positively with respect to the node B. The node B is connected to the input of the FET. The diode has a barrier height substantially equal to the activation energy in a deep level trap contained in crystal constituting the FET.