Abstract: A fuel injector inhibiting adhesion of deposits and simultaneously improving durability by a simple configuration is provided. A fuel injector having a valve body provided with a main space receiving fuel and an injection hole and a needle movably supported at the valve body and having a seal part at its front end, in which needle the movement causes the seal part to separate from or contact an inner surface of the valve body and thereby open or close a fuel passage communicating the main space and the injection hole of the valve body, the fuel injector characterized in that the injection hole of the valve body is covered by an injection hole coating comprised of a material with a lower adsorption and reactivity with oxygen compared with the material of the valve body itself, and the seal part of the needle is covered by a seal part coating comprised of a material higher in liquid-repellency compared with the material of the needle itself and not forming a metal surface.

Abstract: The method of manufacturing a vertical magnetic head comprises the steps of: forming a resist pattern including a concave section on a wafer substrate; laminating a plurality of films in the concave section until forming a prescribed multilayer structure of the main magnetic pole; and removing the resist pattern. Inner faces of the concave section are perpendicular to a surface of the wafer substrate. The laminating step includes the sub-steps of: (a) performing a sputtering process, in which particles are perpendicularly sputtered with respect to the surface of the wafer substrate, a plurality of times so as to laminate a plurality of sputtered films in the concave section; and (b) removing the sputtered films, which have been stuck on the resist pattern in the sub-step (a), from the resist pattern. The sub-steps (a) and (b) are repeated until the prescribed multilayer structure is formed.

Abstract: By the method of manufacturing a thin film magnetic head, a magnetic material having a suitable characteristic can be used for manufacturing a magnetic pole and corrosion of the magnetic pole can be prevented. The method comprises: a step of forming a multilayered magnetic pole; a step of forming a stopper layer on the magnetic pole; a step of forming an insulating layer on the stopper layer; a step of polishing the insulating layer, by chemical mechanical polishing process, until an upper face of the stopper layer is exposed; a step of removing the stopper layer, by dry etching process with a reactive gas, until an upper face of the magnetic head is exposed; a step of removing the upper face of the magnetic pole, by dry etching process with an inert gas, until reaching a prescribed depth; and a step of polishing the upper face of the magnetic pole, by chemical mechanical polishing process, until the upper face of the magnetic pole is flattened.

Abstract: An operation control devices and operation methods thereof so as to eliminates the difficulties in such a case of introduction of vacuum sensors and/or inverter control is disclosed. The disclosure relates to a control of plural sets of vacuum pumps. In order to comply with the subjects to overcome the difficulties, the disclosure proposes to utilize current detection approach instead of direct pressure detection approach, while showing how to estimate a vacuum degree achieved under the operation of the pumps as well as presenting a method on the control of the number of pumps. It is also described how organically a current detecting device, a vacuum degree estimating device, a working pump control device and related methods to satisfy the subjects are linked. The usefulness of the disclosure is also revealed.

Abstract: The magnetoresistance is measured for a magnetoresistive layered-structure, such as a spin valve film, prior to formation of an upper shield layer as well as patterning of a lower shield layer. The magnetic influence of the upper and lower shield layers can completely be eliminated during the measurement of the magnetoresistance. The magnetoresistive layered-structure is allowed to reliably receive the magnetic field over a wider range including a lower magnetic field range. It is accordingly possible to measure the magnetoresistance properly reflecting the magnetic characteristic of the magnetoresistive layered-structure. It is possible to find deficiency of a magnetoresistive read element at an earlier stage of the method.

Abstract: The method comprises forming a plurality of wiring pattern layers on the front surface of a substrate. In the process of forming the wiring pattern layers, an insulator protection film keeps covering over the wiring pattern on the back surface of the substrate. When the formation of the wiring pattern layers has been completed on the front surface of the substrate, a penetrating hole is bored in the cured or hardened insulator protection film. The penetrating hole may be utilized as a conductive via or a conductive through hole. A wiring pattern layer is then formed over the hardened insulator protection film on the back surface of the substrate. It is possible to omit an additional process for removing the insulator protection film. The method contributes to further facilitation of production process and further reduction in production cost.

Abstract: The magnetoresistance is measured for a magnetoresistive layered-structure, such as a spin valve film, prior to formation of an upper shield layer as well as patterning of a lower shield layer. The magnetic influence of the upper and lower shield layers can completely be eliminated during the measurement of the magnetoresistance. The magnetoresistive layered-structure is allowed to reliably receive the magnetic field over a wider range including a lower magnetic field range. It is accordingly possible to measure the magnetoresistance properly reflecting the magnetic characteristic of the magnetoresistive layered-structure. It is possible to find deficiency of a magnetoresistive read element at an earlier stage of the method.

Abstract: A multi-layer wiring substrate includes a main substrate and a plurality of insulating films stacked on the main substrate. The plurality of insulating films have wiring patterns formed on wiring regions thereof and dummy wiring patterns formed on peripheral regions of the wiring regions. The wiring patterns include signal wiring patterns, power supply wiring patterns, and vias. The dummy wiring patterns correspond to the wiring patterns, respectively.

Abstract: In an N-bit address trap comparator, an N-bit address trap register stores an N-bit reference address, a bit-by-bit comparator compares an N-bit address with the N-bit reference address bit-by-bit, and an all-bit comparator detects whether or not all outputs of the bit-by-bit comparator have the same value. In a test mode the N-bit reference address is reset so that a first bit of the N-bit reference address is caused to be a first binary value and other bits are caused to be a second binary value. Also, the second binary value is set in all bits of the N-bit address, and then, the N-bit reference address is shifted within the N-bit address trap register.

Abstract: To operate faster, a memory system includes a central processing unit (CPU) for executing a first instruction, and for outputting first, second and third signals, a memory device for storing first data and the first instruction, a first buffer for storing second data, a controller for writing the second data into the memory device when the controller receives the first signal, for reading the first data from the memory device after writing the second data into the memory device when the controller receives the second signal, and for reading the first instruction from the memory device and sending the first instruction to the CPU before writing the second data into the memory device when the controller receives the third signal.

Abstract: A method for forming bumps including the steps of forming bumps on a dummy wafer. The dummy wafer is diced into dummy chips and the bumps formed on the dummy chips are inspected. Thus only good bumps are transferred to a real chip on which circuit patterns are formed.

Abstract: A multi-layer film substrate comprising at least two laminated insulating layers composed of a polyimide having a low thermal expansion, wherein an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide is interposed between the low thermal expansion polyimide layers. The substrate is produced by laminating at least two insulating layers composed of a polyimide having a low thermal expansion, wherein the low thermal expansion polyimide layers are laminated through an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide.

Abstract: A thin film multi-layer structure includes a plurality of metal thin film layers, and a plurality of layers made of polyimide. The plurality of metal thin film layers and the plurality of layers made of polyimide are stacked in a predetermined order, the plurality of layers made of polyimide being grouped into a first group and a second group including at least a layer located at a top of the plurality of layers. A Young's modulus value of the polyimide of which each layer in the second group is made is less than that of the polyimide of which each layer in the first group is made and a thermal expansion coefficient of the polyimide of which each layer in the first group is made is less than that of the polyimide of which each layer in the second group is made.

Abstract: A multilayer structure is fabricated by forming a conductive layer on an insulative substrate. A first conductive pattern is formed on the first conductive layer and a resist layer having a via hole therethrough is formed on the first pattern. A via lead is formed in the via hole by electrically plating a metal therein utilizing the first layer as a lead for the plating process. The resist and the exposed part of the first layer are removed and a polyimide layer having a thermal expansion coefficient that is equal to that of the via lead is formed over the substrate. The surface of the polyimide layer is etched until the via lead top segment protrudes to a predetermined height above the surface of the etched polyimide layer. A second pattern is formed on the polyimide layer and the exposed lead segment by a plating process.

Abstract: A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor.

Abstract: A method of producing a thin film multi-layered substrate involving the steps of subjecting a copper wiring formed on a substrate to chromate treatment with an aqueous solution containing potassium bichromate or sodium bichromate as a principal component and containing chromic anhydride blended therewith, forming an interlevel insulating film consisting of photosensitive polyimide on the copper wiring, and exposing and developing the photosensitive polyimide film to form a pattern. A miniature pattern can be formed at a high speed and with high production yield.

Abstract: A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Abstract: A method of forming a conductive pattern layer structure includes providing an insulating member containing polyimide, forming a patterned thin film on the insulating member, and forming a patterned conductive layer on the thin film. The patterned conductive layer contains copper. Further, a barrier layer can be patterned to cover an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Abstract: A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Abstract: A multilayer structure of the invention is fabricated by patterning a first electrically conductive layer on an insulative substrate; coating a polyamic acid resin layer all over the first electrically conductive layer; piercing a metal pin into the resin layer so that a first end of the pin contacts and is cold-welded to the first electrically conductive layer; hardening said polyamic acid resin to become polyimide resin; and patterning a second electrically conductive layer over the resin layer and the second end of the pin exposed from the surface of the resin layer. The cold-welding of the pin to the first conductive layer allows a reliable connection thereof. Moreover, this structure and method allow an improved flatness of each layer, resulting in an achievement of a larger number of the multilayers without the prior art problem of pattern breakage caused from less flat layers.