Abstract: A serial data transfer apparatus is provided with a counter 7 for counting the frequency clocks DCLK as the number of clocks of the transfer clocks TCLK, a decoder 8 for detecting the count value CV1 of the counter 7, a transfer interval timer 9 for counting a transfer interval, and with a control circuit 10, wherein the transfer interval timer 9 is made to start counting the frequency clocks DCLK at the time of the last transfer clocks TCLK, i.e., a value of one count before the last count of the counter 7 is detected by the decoder 8. When the transfer interval timer 9 has finished its counting of clock pulses, the control circuit 10 makes the counter 7 start counting the frequency dividing clocks DCLK as well as making the transfer clock output circuit 11 output the next transfer clock TCLK.