Patents by Inventor Kazuaki Takai
Kazuaki Takai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040113189Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.Type: ApplicationFiled: October 29, 2003Publication date: June 17, 2004Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
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Patent number: 6710422Abstract: A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.Type: GrantFiled: August 6, 2002Date of Patent: March 23, 2004Assignee: Fujitsu LimitedInventors: Yukinobu Hikosaka, Akio Itoh, Kazuaki Takai, Takeyasu Saito
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Patent number: 6706540Abstract: There is provided a semiconductor device which includes a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.Type: GrantFiled: February 11, 2003Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Yukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai
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Publication number: 20030230773Abstract: A ferroelectric capacitor having a ferroelectric layer and a pair of electrodes, in which the ferroelectric layer contains carbon or carbon atoms of 5×1018cm−3 or less, and the pair of electrodes is formed by a MOCVD (Metal Organic Chemical Vapor Deposition) method. A process for manufacturing a ferroelectric capacitor having the steps of forming a ferroelectric layer on one of a pair of electrodes; heating the layer at a temperature higher than when forming the layer, and to form the other electrode on the ferroelectric layer, or the steps of forming a ferroelectric layer on one of a pair of electrodes; forming the other electrode on the ferroelectric layer; and heating the layer at a temperature higher than when forming the layer to form the other electrode on the ferroelectric layer, to control carbon atoms of the ferroelectric layer to be 5×1018cm.Type: ApplicationFiled: February 21, 2003Publication date: December 18, 2003Applicant: FUJITSU LIMITEDInventors: Yoshimasa Horii, Osamu Matsuura, Katsuyoshi Matsuura, Kazuaki Takai
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Publication number: 20030148579Abstract: There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.Type: ApplicationFiled: February 11, 2003Publication date: August 7, 2003Applicant: FUJITSU LIMITEDInventors: Yukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai
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Publication number: 20030127703Abstract: A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.Type: ApplicationFiled: August 6, 2002Publication date: July 10, 2003Applicant: Fujitsu LimitedInventors: Yukinobu Hikosaka, Akio Itoh, Kazuaki Takai, Takeyasu Saito
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Patent number: 6570203Abstract: There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.Type: GrantFiled: March 29, 2001Date of Patent: May 27, 2003Assignee: Fujitsu LimitedInventors: Yukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai
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Patent number: 6495412Abstract: A semiconductor device having a ferroelectric capacitor is formed by the steps of forming a lower electrode on a substrate, applying a rapid thermal annealing process to the lower electrode, depositing, after the step of rapid thermal annealing process, a ferroelectric film on the lower electrode, crystallizing the ferroelectric film by applying a thermal annealing process to the ferroelectric film, and forming an upper electrode on the ferroelectric insulation film.Type: GrantFiled: September 10, 1999Date of Patent: December 17, 2002Assignee: Fujitsu LimitedInventors: Sha Zhu, Hideyuki Noshiro, Kazuaki Takai, Hideaki Yamauchi
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Patent number: 6469333Abstract: A semiconductor device includes a ferroelectric capacitor and a protective film of Al2O3 for blocking penetration of H2 atmosphere into the ferroelectric capacitor, wherein the Al2O3 protective film has a density of about 3.0 g/cm3 or more when the thickness of said protective film exceeds about 20 nm and a density of about 3.1 g/cm3 or more when the thickness of the protective film is about 20 nm or less.Type: GrantFiled: March 30, 2000Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventors: Kazuaki Takai, Kouji Tani
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Publication number: 20020061620Abstract: There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.Type: ApplicationFiled: March 29, 2001Publication date: May 23, 2002Applicant: Fujitsu LimitedInventors: Yukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai
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Patent number: 6356475Abstract: A method of reading data from a ferroelectric memory has a memory cell which uses a ferroelectric capacitor as a storage medium. The method includes the steps of (a) applying first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and (b) reading out the data stored in the memory cell by detecting a variation of the polarization of the ferroelectric capacitor.Type: GrantFiled: November 24, 1997Date of Patent: March 12, 2002Assignee: Fujitsu LimitedInventors: Tetsuro Tamura, Kazuaki Takai, Shigenobu Taira
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Publication number: 20010012659Abstract: The semiconductor device comprises an impurity diffusion layer formed on a semiconductor substrate, an insulating film for covering the impurity diffusion layer, a capacitor formed on the insulating film and consisting of a lower electrode, an oxide dielectric film, and an upper electrode, an interlayer insulating film for covering the capacitor, two opening portions formed in the interlayer insulating film to expose the impurity diffusion layer and the upper electrode, a local interconnection formed in two opening portions, and on the interlayer insulating film in a range containing at least a region where the upper electrode contacts the oxide dielectric film, and another interlayer insulating films for covering the local interconnection.Type: ApplicationFiled: May 28, 1999Publication date: August 9, 2001Applicant: FUJITSU LIMITEDInventors: NAOYA SASHIDA, KAZUAKI TAKAI, MITSUHIRO NAKAMURA, TATSUYA YAMAZAKI
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Patent number: 6188090Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: February 20, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 6169305Abstract: The semiconductor device comprises an electrode 36 including a first conductive film 30 formed of an oxide film of a first metal, a second conductive film 32 formed on the first conductive film 30 and formed of the first metal, and a third conductive film 34 formed on the second conductive film 32 and containing a second metal different form the first metal. The second conductive film is sandwiched between the first conductive film and the third conductive film, whereby adhesion of the third conductive film can be improved, and the release of the third conductive film can be prevented.Type: GrantFiled: July 7, 1999Date of Patent: January 2, 2001Assignee: Fujitsu LimitedInventors: Kazuaki Takai, Kazuaki Kondo
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Patent number: 5834362Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: March 21, 1996Date of Patent: November 10, 1998Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 5402748Abstract: A method of fabricating a semiconductor device comprises the steps of growing a first layer of a group III-V compound semiconductor material on a substrate by a vapor phase deposition process by setting the temperature at a first temperature, raising the temperature from the first temperature to a second, higher temperature, growing a second layer of a group III-V compound semiconductor material on the first layer, wherein the step of raising the temperature is conducted while supplying a source gas for the group V element under a condition, determined in terms of a total pressure and a partial pressure of the source gas, such that the condition falls within a region defined by a first condition wherein the total pressure is set to 76 Torr and the partial pressure is set to 0.35 Torr, a second condition wherein the total pressure is set to 760 Torr and the partial pressure is set to 0.6 Torr, a third condition wherein the total pressure is set to 760 Torr and the partial pressure is set to 5.Type: GrantFiled: April 8, 1993Date of Patent: April 4, 1995Assignee: Fujitsu LimitedInventors: Kazuaki Takai, Takashi Eshita