Patents by Inventor Kazuaki Tanida

Kazuaki Tanida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data/clock recovery circuit for recovering data and clock signal with high accuracy
    Patent number: 7120216
    Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
    Inventors: Hiroshi Shirota, Ryosuke Okuda, Katsuya Mizumoto, Kazuaki Tanida
  • Data transfer device for transferring data between blocks of different clock domains
    Patent number: 6911843
    Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: June 28, 2005
    Assignees: Renesas Technology Corp., Mitsubishi Electric System, LSI Design Corporation
    Inventors: Katsuya Mizumoto, Hiroshi Shirota, Ryosuke Okuda, Kazuaki Tanida
  • Data transfer device for transferring data between blocks of different clock domains
    Publication number: 20040027167
    Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.
    Type: Application
    Filed: January 28, 2003
    Publication date: February 12, 2004
    Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, MITSUBISHI ELECTRIC SYSTEM LSI DESIGN CORPORATION
    Inventors: Katsuya Mizumoto, Hiroshi Shirota, Ryosuke Okuda, Kazuaki Tanida
  • Data/clock recovery circuit for recovering data and clock signal with high accuracy
    Publication number: 20030142773
    Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.
    Type: Application
    Filed: July 12, 2002
    Publication date: July 31, 2003
    Inventors: Hiroshi Shirota, Ryosuke Okuda, Katsuya Mizumoto, Kazuaki Tanida