Patents by Inventor Kazuaki Tsunoda
Kazuaki Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125968Abstract: An estimation device collects sensor data representing a change in a load along a time series as a change in a voltage value from a sensor that generates a voltage when a load applied to an area changes, and estimates a matter related to a measurement target passing through a predetermined area by using sensor data collected from the sensor installed in the predetermined area.Type: ApplicationFiled: February 25, 2021Publication date: April 18, 2024Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Sotaro MAEJIMA, Keisuke TSUNODA, Midori KODAMA, Naoki ARAI, Kazuaki OBANA
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Publication number: 20240114684Abstract: A semiconductor memory device includes memory finger structures and a kerf region. The memory finger structures include a first stacked body including conductive layers and semiconductor columns opposed to the conductive layers. The kerf region includes a second stacked body including layers corresponding to at least a part of the conductive layers. A first region in the kerf region is arranged in a first direction with a part of the memory finger structures and includes a part of the second stacked body. A second region in the kerf region is arranged in the first direction with another part of the memory finger structures and does not include the second stacked body. A third region in the kerf region extends in a second direction along an end portion on the memory plane region side in the first direction of the kerf region and includes another part of the second stacked body.Type: ApplicationFiled: June 21, 2023Publication date: April 4, 2024Applicant: Kioxia CorporationInventor: Kazuaki TSUNODA
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Publication number: 20220208782Abstract: According to one embodiment, a semiconductor storage device includes a first stacked body, plate-shaped portions, and a wall portion. The first stacked body, in which electrically conductive layers and first insulating layers are stacked alternately one by one, includes pillar bodies that penetrate the electrically conductive layers in a stacking direction of the electrically conductive layers. The plate-shaped portions extend in a first direction intersecting the stacking direction and divide the first stacked body into blocks. The wall portion includes first and second portions. The first and second portions respectively extend in a second direction intersecting the first direction and the stacking direction and are arranged in the stacking direction. The second portion includes an outer edge connected to a side surface of the first portion and inclined with respect to the staking direction at an angle larger than an angle defined by the side surface and the stacking direction.Type: ApplicationFiled: June 16, 2021Publication date: June 30, 2022Applicant: Kioxia CorporationInventors: Kazuaki TSUNODA, Kazuhiro WASHIDA
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Publication number: 20180277563Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a first insulating film, and a first film. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode films extending in a first direction along an upper surface of the substrate and stacked with spacing from each other. An end part of the stacked body has a stepped shape provided with a terrace for each of the electrode films. The first insulating film is provided on the end part of the stacked body. The first film is provided on the first insulating film, and extends in a direction tilted with respect to the first direction.Type: ApplicationFiled: September 11, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporaionInventors: Kazuaki TSUNODA, Hisakazu MATSUMORI, Taichi IWASAKI
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Patent number: 8507339Abstract: In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor.Type: GrantFiled: November 19, 2010Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Kazuaki Tsunoda
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Patent number: 8089122Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: GrantFiled: January 27, 2010Date of Patent: January 3, 2012Assignee: Panasonic CorporationInventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Publication number: 20110121402Abstract: In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor.Type: ApplicationFiled: November 19, 2010Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi MIYAKE, Kazuaki TSUNODA
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Publication number: 20100127322Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: ApplicationFiled: January 27, 2010Publication date: May 27, 2010Applicant: Panasonic CorporationInventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Patent number: 7709888Abstract: A semiconductor substrate is formed with trenches, and each of the trenches includes: a gate electrode portion in which a gate electrode is arranged; and a gate lead portion which is brought into contact with an interconnect for electrically connecting the gate electrode to the outside. In the gate lead portion for electrically connecting the gate electrode to the outside, an end of each of the trenches has a greater width than a portion of the trench other than the end.Type: GrantFiled: September 29, 2005Date of Patent: May 4, 2010Assignee: Panasonic CorporationInventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Patent number: 7682909Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: GrantFiled: July 2, 2008Date of Patent: March 23, 2010Assignee: Panasonic CorporationInventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Patent number: 7663182Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: GrantFiled: December 9, 2005Date of Patent: February 16, 2010Assignee: Panasonic CorporationInventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Publication number: 20080299727Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: ApplicationFiled: July 2, 2008Publication date: December 4, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Publication number: 20080211017Abstract: A semiconductor substrate is formed with trenches, and each of the trenches includes: a gate electrode portion in which a gate electrode is arranged; and a gate lead portion which is brought into contact with an interconnect for electrically connecting the gate electrode to the outside. In the gate lead portion for electrically connecting the gate electrode to the outside, an end of each of the trenches has a greater width than a portion of the trench other than the end.Type: ApplicationFiled: September 29, 2005Publication date: September 4, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Publication number: 20060124996Abstract: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.Type: ApplicationFiled: December 9, 2005Publication date: June 15, 2006Inventors: Shuji Mizokuchi, Kazuaki Tsunoda
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Patent number: 5815762Abstract: A development processing apparatus includes a processing unit for storing a substrate S and a processing solution supply nozzle arranged above the substrate S stored in the processing unit. A processing solution storage is formed inside the supply nozzle. A supply passage for supplying the processing solution into the solution storage is connected to the supply nozzle. A plurality of eject holes for ejecting the processing solution in the solution storage are formed in a lower surface of the supply nozzle. In this processing apparatus, the upper surface of the solution storage consists of at least one inclined surface, and an exhaust port is formed in a high portion of the inclined surface.Type: GrantFiled: June 19, 1997Date of Patent: September 29, 1998Assignee: Tokyo Electron LimitedInventors: Mitsuhiro Sakai, Masafumi Nomura, Kazuaki Tsunoda
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Patent number: 5254951Abstract: A current measuring circuit for measuring discharging current and charging current of a battery, which is selectively connected to a load and a charger. The current measuring circuit comprises a resistor connected in series with the battery having a sufficiently low resistance value as not to substantially restrain the output current from the battery and a differential amplifier for amplifying a potential difference between both ends of the resistor. By providing a switch for short-circuiting one input terminal and the other input terminal of the differential amplifier, an offset/drift voltage of the differential amplifier can be obtained. This offset/drift voltage is used for correcting the output voltage from the differential amplifier at the time of current measurement and, thereby, the discharging current and charging current of the battery can be measured accurately.Type: GrantFiled: May 27, 1992Date of Patent: October 19, 1993Assignee: Fujitsu LimitedInventors: Seiji Goto, Kazuaki Tsunoda, Yukio Murayama