Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into the semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an erroneous operation from developing when the power source is closed, provision is made of a power source closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is being applied to the memory element from the time from when the power source circuit is closed up to the times when the read operation mode is designated by an external control signal.