Abstract: A check is made to determine whether there is identity among set membership functions, different numbers are assigned to mutually different membership functions, and identical numbers are assigned to membership functions which are mutually identical. These membership functions are stored in memory in correlation with their numbers, labels and the names of input or output variables.

Abstract: All data to be compared are stored in a register group (1) in advance. When a MIN operation is executed, a maximum value (e.g, FF) is initially set in a memory (2). Source data outputted by the register group (1) and destination data outputted by the memory (2) are applied to a full adder/subtractor (30) operating as a subtractor. The subtractor (30) outputs a borrow signal when an item of source data is smaller than an item of destination data. In response to the borrow signal, an AND gate (33) is enabled, so that the item of source data is written in the memory (2) as a new item of destination data. When an item of source data is equal to or greater than an item of destination data, the borrow signal is not delivered as an output, the AND gate (33) is disabled and a new item of data is not stored in the memory (2). The foregoing operation is repeated with regard to all data in the register group (1).

Abstract: In a fuzzy controller comprising a fuzzy inference device for subjecting one or a plurality of input signals to fuzzy inference operations using membership functions in accordance with a predetermined rule and outputting a non-fuzzy value determined on the basis of the results of the inferences, there are provided an input signal level converter for converting signal levels of the input signals on the input side of the fuzzy inference device and an output signal level converter for converting a signal level of the output signal on the output side of the fuzzy inference device.

Abstract: A fuzzy computer system has: a digital processor; a digital memory; a fuzzy inference processing circuit; and an interface for the fuzzy inference processing circuit. The digital memory stores programs executed by the digital processor and inference rules used by the fuzzy inference processing circuit. The fuzzy inference processing circuit executes a fuzzy inference on the basis of a given inference rule. The interface connects the digital processor and the fuzzy inference processing circuit through a bus. The digital processor gives the inference rules stored in the digital memory to the fuzzy inference processing circuit through the interface and fetches the result of the inference of the fuzzy inference processing circuit through the interface.

Abstract: A count control apparatus for controlling a photocopying machine is constructed to be enabled by a copy command signal to effect repetitive photocopying operations and to generate a sheet number pulse for each photocopying operation wherein a desired number of sheets being photocopied by said photocopying machine is preset by a keyboard or the like. The sheet number pulses are counted, the preset number is compared with the count number, and the copy command signal is generated in response to a comparison of the count value with the preset value. Normally the copy command signal is conditioned by a comparison of the count number with the preset number. However the copy command signal is prevented from being conditioned by the comparison in response to a manual changing of the presetting whereby the copy command signal is conditioned in a different manner during the changing of the presetting, whereby a differently conditioned copy command signal is provided.

Abstract: An apparatus for displaying numerical value information, comprising: a first display having a plurality of digit display positions each capable of selectively displaying one of Arabic numerals; a second display having a plurality of digit display positions each capable of selectively displaying one of Arabian language numerals; a digit timing signal generator; a first and second digit drivers responsive to said digit timing signals for enabling said digit display positions of each of said first and second displays, respectively, in a digit timing sequence; a re-circulation shift register operable responsive to said digit timing signals for storing a signal representing multi-digit numerical value information comprising a plurality of digit numeral signals each representing in a bit-coded manner a value of the numeral to be displayed in the corresponding digit display position in said displays; a first converter coupled to a predetermined digit position of said register for withdrawing in said digit timing seq

Abstract: A keying input apparatus is provided which includes; a bit pattern generator responsive to a clock signal for generating different bit patterns of four bits, in a bit sequence and a decoding matrix for converting the different bit patterns at every fourth bit, into individual digit timing signals. A plurality of key switches are connected at one end thereof with corresponding ones of the digit timing signals and connected to a common terminal at the other ends thereof, to drive a gate responsive to the common connected output of said key switches for allowing a coded signal representative of a particular depressed key to be withdrawn from the bit pattern generator and transfer it to a circulation register for storing the coded signal. Depression of a given key thus enables the gate at a corresponding digit timing to load a coded signal corresponding to that digit timing in the register, so that the coded signal as stored in the register uniquely identifies the depressed key.

Abstract: A keying input apparatus operates as a function of two kinds of timing signals, one being of a first timing period and generally composed of a plurality of digit timing signals generated in a digit sequence and the other being of a second timing period for disabling a display device during that period, such that a plurality of pieces of information, such as the digit timing signals and/or segment selection signals for the display device, are provided from a plurality of output terminals during said first timing signal for the purpose of outputting thereof to the display device, and a plurality of different coded signals, each composed of a plurality of bits, in a bit sequence, are provided from the same said plurality of output terminals during said second timing signal, each of which output terminals is individually connected to a corresponding one of a plurality of key switches, which are commonly connected through a common terminal to a register, so that any desired coded signal, as selected by a correspon

Abstract: In a fuzzy controller comprising a fuzzy inference device for subjecting one or a plurality of input signals to fuzzy inference operations using membership functions in accordance with a predetermined rule and outputting a non-fuzzy value determined on the basis of the results of the inferences, there are provided an input signal level converter for converting signal levels of the input signals on the input side of the fuzzy inference device and an output signal level converter for converting a signal level of the output signal on the output side of the fuzzy inference device.