Patents by Inventor Kazuaki Yamane

Kazuaki Yamane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and system
    Patent number: 8542041
    Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: September 24, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mitsuhiro Ogai, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
  • SEMICONDUCTOR DEVICE AND SYSTEM
    Publication number: 20100253419
    Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Mitsuhiro OGAI, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima