Patents by Inventor Kazuaki Yamazaki

Kazuaki Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6373129
    Abstract: A semiconductor apparatus includes a plurality of semiconductor units and a common gate liner having silicon chip resistors at portions corresponding to the semiconductor units. Each unit includes a semiconductor chip, a collector base plate fixed to the chip, an insulative positioning guide, an emitter contact terminal, and a contact probe having two distal contact ends. The positioning guide positions the emitter contact terminal on the emitter electrode and the contact probe on a gate pad. The semiconductor units are collectively held by the gate liner such that the contact probes press the respective silicon chip resistors and the respective gate pads. The individual positioning guide prevents dislocation of the contact probe and the gate pad. The semiconductor apparatus simplifies the gate wiring and improves the precise positioning of the constituent elements and the reliability of the apparatus. The package size is reduced as well.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: April 16, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuaki Yamazaki, Yoshikazu Takahashi
  • Patent number: 6181007
    Abstract: A semiconductor device is provided which includes a plurality of semiconductor units each including a semiconductor chip, a support plate, a contact terminal block and a positioning guide, a flat package including a pair of common electrode plates and an insulating outer sleeve, and positioning and thermal-stress reducing means for positioning the support plates of the semiconductor elements in a horizontal direction, without interfering with the positioning guides, and reducing a thermal stress applied to a peripheral portion of a contact interface between the contact terminal block and the semiconductor chip due to heat generated during intermittent flow of current through a load. The contact terminal block is disposed on a first main electrode of the semiconductor chip, while the support plate is secured to a second main electrode of the chip, such that the semiconductor chip is placed under pressure between the contact terminal block and support plate that also serve as conductors and heat radiators.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: January 30, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuaki Yamazaki, Yoshikazu Takahashi