Patents by Inventor Kazufumi Suzukawa
Kazufumi Suzukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100157689Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: March 5, 2010Publication date: June 24, 2010Inventors: TOSHIHIRO TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7700992Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: June 19, 2008Date of Patent: April 20, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20090052238Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: October 27, 2008Publication date: February 26, 2009Inventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20090010072Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: June 19, 2008Publication date: January 8, 2009Inventors: Toshihiro TANAKA, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7414283Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: May 2, 2006Date of Patent: August 19, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7376015Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: August 5, 2005Date of Patent: May 20, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Patent number: 7342826Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: GrantFiled: March 2, 2007Date of Patent: March 11, 2008Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
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Publication number: 20070247918Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: August 30, 2004Publication date: October 25, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20070153618Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: ApplicationFiled: March 2, 2007Publication date: July 5, 2007Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
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Patent number: 7190615Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: GrantFiled: March 29, 2004Date of Patent: March 13, 2007Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
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Publication number: 20060220100Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: May 2, 2006Publication date: October 5, 2006Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 7072218Abstract: A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver has in a current path of the high voltages, a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is switched to an off-state first and the other transistor is switched to an on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already shut off, and therefore the high voltage output driver does not break down.Type: GrantFiled: July 3, 2002Date of Patent: July 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masamichi Fujito, Yuko Nakamura, Kazufumi Suzukawa, Toshihiro Tanaka, Yutaka Shinagawa
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Patent number: 7057230Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: July 22, 2002Date of Patent: June 6, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20050265114Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: ApplicationFiled: August 5, 2005Publication date: December 1, 2005Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Publication number: 20050258474Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: July 22, 2002Publication date: November 24, 2005Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Patent number: 6963507Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: April 21, 2003Date of Patent: November 8, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Publication number: 20040212014Abstract: There are included a high voltage output driver (1) which derives operational power from high voltages and a switching circuit (2) which reverses the output state of the high voltage output driver. The high voltage output driver includes on a current path of the high voltages a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is turned to the off-state first and another transistor is turned to the on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already cut off, and therefore the high voltage output driver does not break down.Type: ApplicationFiled: February 12, 2004Publication date: October 28, 2004Inventors: Masamichi Fujito, Yuko Nakamura, Kazufumi Suzukawa, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20040202020Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: ApplicationFiled: March 29, 2004Publication date: October 14, 2004Applicant: Renesas Technology Corp.Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
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Publication number: 20030206451Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “1” (or logic “1) is successively performed.Type: ApplicationFiled: April 21, 2003Publication date: November 6, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Patent number: 6567313Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: September 28, 2001Date of Patent: May 20, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri