Abstract: When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it is detected at what digit positions in intermediate data in an intermediate data holding circuit 30 data elements which are to be finally output as output data from the second shift circuit 50 are located. Based on a result of the detection of digit positions by the decoding circuit 20, the intermediate data holding circuit 30 holds only data elements to be finally output, among data elements in the intermediate data, and does not hold unnecessary data elements which are not included in the output data. Therefore, by controlling a data storage operation in the intermediate data holding circuit 30, an increase in power due to the pipeline structure is suppressed.

Abstract: An interleaving/deinterleaving method and apparatus may interleave/deinterleave first data to produce second data so that the arrangement of data elements of the second data is different from that of the first data. To accomplish this, word data that are part of the first data are read from a data storage section and a data element to be processed is selected from the word data for output. The operations of reading word data and selecting data elements of the word data to output are repeated, and a sequence of data elements to be processed at the time of repetition is determined in accordance with the arrangement of the data elements of the second data.

Abstract: There is provided a multiplication apparatus for generating a product of a multiplicand and a multiplier, each of which is a fixed point number represented in two's complement. The multiplication apparatus has an encoding unit for encoding the multiplier based on the radix-4 Booth's algorithm and outputting a plurality of encoding results obtained, an overflow detection unit for detecting an occurrence of an overflow when each of the multiplicand and the multiplier is a negative maximum value, and a partial product generation unit for generating a plurality of partial products from the multiplicand and the plurality of encoding results as well as a plurality of correction factors corresponding to the plurality of partial products and outputting the plurality of partial products and the plurality of correction factors.

Abstract: When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it is detected at what digit positions in intermediate data in an intermediate data holding circuit 30 data elements which are to be finally output as output data from the second shift circuit 50 are located. Based on a result of the detection of digit positions by the decoding circuit 20, the intermediate data holding circuit 30 holds only data elements to be finally output, among data elements in the intermediate data, and does not hold unnecessary data elements which are not included in the output data. Therefore, by controlling a data storage operation in the intermediate data holding circuit 30, an increase in power due to the pipeline structure is suppressed.

Abstract: Conventionally, when interleaving/deinterleaving was carried out in bit units, complicated logical operation processing was required, thereby causing a problem of increasing the size of the circuit and the number of processing steps. In the present invention, address information and bit position information output from access information supply means are determined in accordance with the arrangement of data elements obtained after interleaving/deinterleaving. From the address, corresponding to the address information from the access information supply means, of data storage means, 1-word data is read, and the data element in the bit position designated by the bit position information from the access information supply means is selected and output. The bit sequence obtained by the above-mentioned continuous processing has already become a data sequence obtained after interleaving/deinterleaving.

Abstract: In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result.