Abstract: A video recording medium, video signal processor, and method are provided. The video signal processor includes a transcoder for receiving a video input signal comprising a plurality of input signal frames, each of the input signal frames including at least one of intraframe data and interframe data, and for constructing a corresponding plurality of system frames from the input signal frames, each of the system frames having a fixed length and including a first portion, having a first fixed length, including intraframe data and excluding interframe data, and a second portion, having a second fixed length, including interframe data and excluding intraframe data.

Abstract: A band compression signal processor including a band compression circuit for intra-frame-coding and inter-frame-coding an input video signal which forms a picture areas, inter-frame-coding the input video signal which is intra-frame-coded, and repeating the above signal processing adaptively according to a motion evaluation on the input video signal, and a refresh coding circuit for periodically intra-frame-coding signals corresponding to b areas of the a areas for each frame at a period of f frames. A macro-block is formed by adding overhead data indicating the contents of variable length codes of a refresh block and a non-refresh block to the refresh block which has undergone the refresh coding and the non-refresh block which has not undergone the refresh coding.

Abstract: A band compression signal processor designed to convert video signals or the like into digital signals and to perform band compression by effecting both intra-frame encoding and inter-frame encoding. The signal output by the processor is supplied to a recording/reproducing apparatus. In the apparatus, the signal is recorded on a magnetic tape and reproduced therefrom by helical scanning method. The signal intra-frame-encoded is arranged within such a region as to be read out in fast reproduction mode.

Abstract: An encoder separates an input digital signal including m bits into the first group and the second group, and encodes each piece of data in the first group to a single code word including n bits in one-to-one correspondence and encodes each piece of data in the second group to two code words each including n bits in one-to-two correspondence. A CDS calculator calculates a CDS value for each of the words output from the encoder. A DSV calculator calculates the accumulated DSV value of the individual words output from the encoder. When the two-n-bit code words are output from the encoder, a code selector selects that one of the code words which decreases the next accumulated DSV value to be calculated by the DSV calculator, according to the CDS value from the CDS calculator and the accumulated DSV value from the DSV calculator.

Abstract: A non-linear amplifier circuit comprises a low band eliminating filter for receiving an input signal from an input terminal, a logarithmic amplifier and an adder for adding the output signal of this logarithmic amplifier and the input signal with a predetermined polarity relationship to produce an output signal and sending this output signal to an output terminal. The logarithmic amplifier comprises an amplifier for receiving the output signal of the low band eliminating filter, a bidirectional logarithmic element and a resistor coupled in parallel thereto between the input and output terminals of the amplifier.