Patents by Inventor Kazuharu YAMABE
Kazuharu YAMABE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230397414Abstract: A semiconductor device includes a substrate, and a stacked film provided above the substrate and including a plurality of electrode layers separated from each other in a first direction. The device further includes an array region provided on the substrate and including a memory cell array having a plurality of word lines and a plurality of select lines that constitute the plurality of electrode layers. The device further includes a first plug region provided on the substrate, located in a second direction of the array region, and including a first contact plug electrically connected to a first select line of the plurality of select lines. The device further includes a second plug region provided on the substrate, located in the second direction of the first plug region, and including a second contact plug electrically connected to a first word line of the plurality of word lines.Type: ApplicationFiled: March 1, 2023Publication date: December 7, 2023Applicant: Kioxia CorporationInventors: Takeshi MURATA, Kazuharu YAMABE
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Patent number: 11521687Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.Type: GrantFiled: May 7, 2021Date of Patent: December 6, 2022Assignee: KIOXIA CORPORATIONInventors: Kazuharu Yamabe, Qianqian Xu
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Publication number: 20220285391Abstract: In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body.Type: ApplicationFiled: August 26, 2021Publication date: September 8, 2022Applicant: Kioxia CorporationInventors: Kazuharu YAMABE, Yoshiro SHIMOJO
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Publication number: 20220068949Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region.Type: ApplicationFiled: March 3, 2021Publication date: March 3, 2022Inventor: Kazuharu YAMABE
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Patent number: 11264105Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.Type: GrantFiled: August 14, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Kazuharu Yamabe, Yoichi Minemura
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Publication number: 20210280256Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.Type: ApplicationFiled: August 14, 2020Publication date: September 9, 2021Applicant: Kioxia CorporationInventors: Kazuharu YAMABE, Yoichi MINEMURA
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Publication number: 20210264984Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: Kazuharu YAMABE, Qianqian XU
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Patent number: 11004514Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.Type: GrantFiled: March 3, 2020Date of Patent: May 11, 2021Assignee: KIOXIA CORPORATIONInventors: Kazuharu Yamabe, Qianqian Xu
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Publication number: 20210082512Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.Type: ApplicationFiled: March 3, 2020Publication date: March 18, 2021Inventors: Kazuharu YAMABE, Qianqian XU
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Patent number: 10593696Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: GrantFiled: May 10, 2019Date of Patent: March 17, 2020Assignee: Toshiba Memory CorporationInventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Patent number: 10510417Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.Type: GrantFiled: August 13, 2018Date of Patent: December 17, 2019Assignee: Toshiba Memory CorporationInventors: Kazuharu Yamabe, Tatsuo Izumi
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Publication number: 20190287622Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.Type: ApplicationFiled: August 13, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Kazuharu YAMABE, Tatsuo IZUMI
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Publication number: 20190273093Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: ApplicationFiled: May 10, 2019Publication date: September 5, 2019Applicant: Toshiba Memory CorporationInventors: Kazuharu YAMABE, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Patent number: 10332904Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: GrantFiled: March 13, 2017Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
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Publication number: 20180083027Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.Type: ApplicationFiled: March 13, 2017Publication date: March 22, 2018Applicant: Toshiba Memory CorporationInventors: Kazuharu YAMABE, Ryota SUZUKI, Tatsuo IZUMI, Masahiro FUKUDA, Takuo OHASHI
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Patent number: 9508554Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: GrantFiled: September 29, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Kazuharu Yamabe, Shinichiro Abe, Shoji Yoshida, Hideaki Yamakoshi, Toshio Kudo, Seiji Muranaka, Fukuo Owada, Daisuke Okada
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Publication number: 20160093499Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: ApplicationFiled: September 29, 2015Publication date: March 31, 2016Inventors: Kazuharu YAMABE, Shinichiro ABE, Shoji YOSHIDA, Hideaki YAMAKOSHI, Toshio KUDO, Seiji MURANAKA, Fukuo OWADA, Daisuke OKADA