Abstract: According to one embodiment, an electronic device includes a display panel and an image sensor element, the display panel includes a first area that does not overlap the image sensor element and a second area that overlaps the image sensor element, the display panel includes a first electrode, a second electrode that overlaps the first electrode, and a liquid crystal layer, the second electrode includes a plurality of first slits provided in the first area and a plurality of second slits provided in the second area, the second electrode includes a plurality of first slits provided in the first area and a plurality of second slits provided in the second area, the plurality of second slits are arranged based on a Fibonacci sequence.

Abstract: A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectively received signal to the immediately succeeding unit circuit. The selection-delay unit circuit is only formed of three transfer gates and two inverters in order to reduce a chip size and save power consumption.

Abstract: Disclosed is a monostable multivibrator in which an output voltage of an integrating circuit and a reference voltage from a reference voltage source are compared by means of a comparator, and a flip-flop is set in response to a comparison voltage of the comparator and reset in response to an external reset signal. The output of the flip-flop operates a transistor for controlling the discharge of a capacitor of the integrating circuit, and is taken out as an output pulse of the monostable multivibrator.

Abstract: A voltage comparator suitable for use in an analog-to-digital converter such as a successive-approximation converter, and provided with capacitively cascade-connected inverter stages to produce an output signal of a logic level 1 or 0 according to the relationship between the magnitudes of two analog input voltage signals to be compared. A first series circuit of an MOS switching transistor and resistive element is connected between the input and output of the respective inverters; a second series circuit of a MOS switching transistor and resistive element is connected between the input of each inverter and circuit ground. The MOS transistors of the first and second series circuits are simultaneously enabled or disabled by a clock pulse; and two input voltage signals to be compared are alternately applied to the first stage coupling capacitor.

Abstract: A voltage comparator suitable for use in an analog-to-digital converter such as a successive-approximation converter which is comprised of a plurality of capacitively cascade-connected inverters to generate an output signal of a logic level 1 or 0 according to the relationship between the magnitudes of two analog input voltage signals to be compared. A bias circuit for impressing a bias voltage on the inputs of the inverters comprises first and second MOS transistor resistor elements connected in series across a power source and a third MOS transistor which is connected in parallel to the second MOS transistor, and whose gate is supplied with a control voltage so that the inverters are respectively biased to the optimum operation point for comparison through adjustment of the control voltage. With another embodiment of this invention, the respective inverters are automatically biased to the optimum operation point for comparison by detection of the bias voltage of inverters.