Abstract: A highly reliable information processor system of the present invention takes in the bus cycle start signals which are output to notify outside devices of the timings where the first to third microprocessors start their bus cycles so as to compare them with each other and, detects any malfunction of a microprocessor based on discrepancy in start timing among bus cycles. When it judges that the first microprocessor in execution mode malfunctions, it logically isolates the first microprocessor operating in execution mode and causes either of the second or third microprocessors operating in monitor mode to enter execution mode. After such degradation from triple-processor configuration to double-processor configuration, it executes again the bus cycle which has been executed at the time of malfunction detection.