Abstract: A microcomputer comprises an arithmetic and logic unit having a pair of input connected to receive a pair of n-bit data and one output for generating a n-bit data of operation result. A NOR circuit is provided to receive the n-bit operation result from the arithmetic and logic unit for generating a signal of a high level when all the bits of the operation result are zero. An output of the NOR circuit is connected to one input of an AND circuit, whose output is connected to a first input of a multiplexor having a second input connected to receive a setting signal for start of coincidence detection operation. Further, there is provided a Z flag having an input connected to an output of the multiplexor and an output connected to the other input of the AND circuit. When the coincidence detection operation is started, the setting signal of a high level is applied through the multiplexor to the Z flag so as to set the Z flag.