Abstract: A video display control circuit includes a reading circuit for reading address data in a video RAM pointer. The video RAM pointer designates an address in a RAM where an address data to be supplied to a character ROM pointer is stored. The character ROM pointer designates an address in a ROM where character data by which characters are displayed on a screen are stored. If the address data read from the video RAM pointer is earlier in access time than a selected address of the video RAM, into which a new address data is required to be re-written, operation of re-writing data of the video RAM is not carried out, so that flickering or momentary black-out of the display caused by the re-writing operation may not occur.

Abstract: An assembler system translates a source program having a plurality of source code modules. The source code modules are evaluated in order to identify which source code module is the first source code module for which:(1) an object code module has not been assembled,(2) the source code module production time is later than the corresponding object code module production time, or(3) the source code module is positioned differently than it is in a recorded order.This first identified source code module, and the source code modules succeeding it, are assembled in accordance with the current assemble order.

Abstract: A computer comprises an instruction memory storing therein instruction codes and including a plurality of divided address spaces, and a CPU receiving an instruction read out of the instruction memory for executing the read-out instruction and outputting an address data for an instruction code to be next executed to the instruction memory. In addition, there is provided a space code memory storing respective codes indicative of the divided address spaces within the instruction memory for respective instruction codes stored in the instruction memory, for generating an address space code for an instruction to be executed next to an instruction code designated by the address given to the instruction memory.

Abstract: An apparatus for use in for a system indicating at least first and second pictures in a screen of a horizontal scan type display, includes a first circuit for measuring the pulse width or duration of a horizontal synchronism signal for the first picture, and a second circuit for determining a horizontal indication start position of the second picture on the basis of the measured pulse width or duration of a horizontal synchronism signal.

Abstract: A semiconductor includes a read only memory associated with an instruction decoder for decoding the instructions read out from the read only memory, and adapted to generate an address load signal when a branch instruction is read out. A program counter is provided to supply the read only memory with the address of a memory location to be read out. This program counter is adapted to be ordinarily incremented at each read-out of the read only memory and to be loaded with the branch address of the read only memory when a branch address load signal is outputted from the instruction decoder. There is also provided a circuit in response to a test mode signal for generating a branch inhibiting signal. A gate is connected to receive the branch inhibiting signal and the branch address load signal, respectively. An output of the gate is connected to an address load control input of the program counter.

Abstract: A synchronization signal generator includes a delayed signal generator receiving an original oscillation signal from a ceaselessly operated oscillator to generate a plurality of delayed signals having different delay times from the original oscillation signal, and a trigger signal generator receiving a synchronization signal for generating a trigger signal. There is provided a selector circuit receiving the delayed signals and the trigger signal for selecting, among the delayed signals, only the delayed signal in synchronism with the trigger signal with a substantially constant delay.

Abstract: A character generator for generating a data signal for a character having an emphasizing contour. The generator includes a memory storing data of a character to be displayed. This data comprising first data representing a contour of the character and second data representing a compressed character data. The first data are stored in a first shift register and shifted in synchronism with a first shift clock, and the second data are stored in a second shift register and shifted in synchronism with a second shift clock having a frequency smaller than that of the first shift clock. A contour signal and a character signal are thereby generated.

Abstract: A nonvolatile memory (programmable) comprises a plurality of logic memories, each of which is composed of a plurality of memory segments. Each of the memory segments is constituted of a first nonvolatile memory area capable of storing data of a predetermined bit number and a second nonvolatile memory area containing an identifier for the corresponding first nonvolatile memory area. Each of the logical memories is given one logical address, and when write operation is executed, a controller operates to access to the logical memory identified by the inputted logical address so as to erase in the accessed logical memory the memory segment having the identifier indicating that the data is stored, and to write the inputted data to the memory segment next to the erased memory segment.

Abstract: A semiconductor device has a first ROM and a second ROM on a single semiconductor chip. To write information in the first ROM, a contact mask pattern is used by which wirings are formed on the chip, while information is written in the second ROM when memory transistors are formed on the chip. The first ROM stores the non-commonly used information of the program to be stored, or a specific user supplied program, and the second ROM stores predetermined and commonly used information of the program to be stored. Thus, a semiconductor device having a fixed memory in which a large capacity of information is stored can be provided to a user within a short period of time.

Abstract: A single chip microcomputer responsive to internal and external instructions in normal and debug modes, respectively, comprises a program counter and first, second, third, and fourth port groups in both of the normal and the debug modes. The first through the fourth port groups are operable in the normal mode to process each internal instruction. Master and slave modes are defined in the debug mode to selectively change operations of the first through the fourth port groups by the use of port controllers to process each external instruction. The master mode is specified by using the first and the second groups as an instruction input port group for each external instruction and as a transfer bus for data related to each external instruction, respectively. In contrast, the third and the fourth port groups are used as an instruction input port group and a transfer bus, respectively. The master and the slave modes are indicated through a single terminal used in the normal mode.